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@@ -1634,60 +1634,75 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
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}
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}
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-static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
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- struct intel_crtc_state *pipe_config,
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- struct drm_connector_state *conn_state)
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+static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
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+ int link_rate, uint32_t lane_count,
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+ struct intel_shared_dpll *pll,
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+ bool link_mst)
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{
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- struct drm_encoder *encoder = &intel_encoder->base;
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- struct drm_i915_private *dev_priv = to_i915(encoder->dev);
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- struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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- enum port port = intel_ddi_get_encoder_port(intel_encoder);
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- int type = intel_encoder->type;
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-
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- if (type == INTEL_OUTPUT_HDMI) {
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- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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-
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- intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
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- }
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+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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+ enum port port = intel_ddi_get_encoder_port(encoder);
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- if (type == INTEL_OUTPUT_EDP) {
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- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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+ intel_dp_set_link_params(intel_dp, link_rate, lane_count,
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+ link_mst);
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+ if (encoder->type == INTEL_OUTPUT_EDP)
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intel_edp_panel_on(intel_dp);
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- }
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-
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- intel_ddi_clk_select(intel_encoder, crtc->config->shared_dpll);
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-
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- if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
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- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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- intel_prepare_dp_ddi_buffers(intel_encoder);
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-
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- intel_dp_set_link_params(intel_dp, crtc->config->port_clock,
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- crtc->config->lane_count,
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- intel_crtc_has_type(crtc->config,
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- INTEL_OUTPUT_DP_MST));
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+ intel_ddi_clk_select(encoder, pll);
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+ intel_prepare_dp_ddi_buffers(encoder);
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+ intel_ddi_init_dp_buf_reg(encoder);
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+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
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+ intel_dp_start_link_train(intel_dp);
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+ if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
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+ intel_dp_stop_link_train(intel_dp);
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+}
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- intel_ddi_init_dp_buf_reg(intel_encoder);
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+static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
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+ bool has_hdmi_sink,
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+ struct drm_display_mode *adjusted_mode,
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+ struct intel_shared_dpll *pll)
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+{
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+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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+ struct drm_encoder *drm_encoder = &encoder->base;
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+ enum port port = intel_ddi_get_encoder_port(encoder);
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+ int level = intel_ddi_hdmi_level(dev_priv, port);
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- intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
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- intel_dp_start_link_train(intel_dp);
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- if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
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- intel_dp_stop_link_train(intel_dp);
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- } else if (type == INTEL_OUTPUT_HDMI) {
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- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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- int level = intel_ddi_hdmi_level(dev_priv, port);
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+ intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
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+ intel_ddi_clk_select(encoder, pll);
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+ intel_prepare_hdmi_ddi_buffers(encoder);
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+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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+ skl_ddi_set_iboost(encoder, level);
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+ else if (IS_BROXTON(dev_priv))
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+ bxt_ddi_vswing_sequence(dev_priv, level, port,
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+ INTEL_OUTPUT_HDMI);
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- intel_prepare_hdmi_ddi_buffers(intel_encoder);
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+ intel_hdmi->set_infoframes(drm_encoder,
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+ has_hdmi_sink,
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+ adjusted_mode);
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+}
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- if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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- skl_ddi_set_iboost(intel_encoder, level);
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- else if (IS_BROXTON(dev_priv))
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- bxt_ddi_vswing_sequence(dev_priv, level, port,
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- INTEL_OUTPUT_HDMI);
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+static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
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+ struct intel_crtc_state *pipe_config,
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+ struct drm_connector_state *conn_state)
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+{
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+ struct drm_encoder *encoder = &intel_encoder->base;
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+ struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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+ int type = intel_encoder->type;
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- intel_hdmi->set_infoframes(encoder,
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- crtc->config->has_hdmi_sink,
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- &crtc->config->base.adjusted_mode);
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+ if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
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+ intel_ddi_pre_enable_dp(intel_encoder,
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+ crtc->config->port_clock,
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+ crtc->config->lane_count,
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+ crtc->config->shared_dpll,
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+ intel_crtc_has_type(crtc->config,
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+ INTEL_OUTPUT_DP_MST));
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+ }
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+ if (type == INTEL_OUTPUT_HDMI) {
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+ intel_ddi_pre_enable_hdmi(intel_encoder,
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+ crtc->config->has_hdmi_sink,
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+ &crtc->config->base.adjusted_mode,
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+ crtc->config->shared_dpll);
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}
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}
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