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@@ -1,487 +0,0 @@
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-/*
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- * PXA2xx SPI private DMA support.
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- *
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- * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- */
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-
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-#include <linux/delay.h>
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-#include <linux/device.h>
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-#include <linux/dma-mapping.h>
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-#include <linux/pxa2xx_ssp.h>
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-#include <linux/spi/spi.h>
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-#include <linux/spi/pxa2xx_spi.h>
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-
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-#include <mach/dma.h>
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-#include "spi-pxa2xx.h"
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-
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-#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
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-#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
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-
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-bool pxa2xx_spi_dma_is_possible(size_t len)
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-{
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- /* Try to map dma buffer and do a dma transfer if successful, but
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- * only if the length is non-zero and less than MAX_DMA_LEN.
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- *
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- * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
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- * of PIO instead. Care is needed above because the transfer may
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- * have have been passed with buffers that are already dma mapped.
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- * A zero-length transfer in PIO mode will not try to write/read
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- * to/from the buffers
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- *
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- * REVISIT large transfers are exactly where we most want to be
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- * using DMA. If this happens much, split those transfers into
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- * multiple DMA segments rather than forcing PIO.
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- */
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- return len > 0 && len <= MAX_DMA_LEN;
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-}
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-
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-int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
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-{
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- struct spi_message *msg = drv_data->cur_msg;
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- struct device *dev = &msg->spi->dev;
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-
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- if (!drv_data->cur_chip->enable_dma)
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- return 0;
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-
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- if (msg->is_dma_mapped)
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- return drv_data->rx_dma && drv_data->tx_dma;
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-
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- if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
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- return 0;
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-
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- /* Modify setup if rx buffer is null */
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- if (drv_data->rx == NULL) {
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- *drv_data->null_dma_buf = 0;
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- drv_data->rx = drv_data->null_dma_buf;
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- drv_data->rx_map_len = 4;
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- } else
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- drv_data->rx_map_len = drv_data->len;
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-
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-
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- /* Modify setup if tx buffer is null */
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- if (drv_data->tx == NULL) {
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- *drv_data->null_dma_buf = 0;
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- drv_data->tx = drv_data->null_dma_buf;
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- drv_data->tx_map_len = 4;
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- } else
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- drv_data->tx_map_len = drv_data->len;
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-
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- /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
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- * so we flush the cache *before* invalidating it, in case
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- * the tx and rx buffers overlap.
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- */
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- drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
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- drv_data->tx_map_len, DMA_TO_DEVICE);
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- if (dma_mapping_error(dev, drv_data->tx_dma))
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- return 0;
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-
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- /* Stream map the rx buffer */
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- drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
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- drv_data->rx_map_len, DMA_FROM_DEVICE);
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- if (dma_mapping_error(dev, drv_data->rx_dma)) {
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- dma_unmap_single(dev, drv_data->tx_dma,
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- drv_data->tx_map_len, DMA_TO_DEVICE);
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- return 0;
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- }
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-
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- return 1;
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-}
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-
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-static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
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-{
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- struct device *dev;
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-
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- if (!drv_data->dma_mapped)
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- return;
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-
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- if (!drv_data->cur_msg->is_dma_mapped) {
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- dev = &drv_data->cur_msg->spi->dev;
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- dma_unmap_single(dev, drv_data->rx_dma,
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- drv_data->rx_map_len, DMA_FROM_DEVICE);
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- dma_unmap_single(dev, drv_data->tx_dma,
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- drv_data->tx_map_len, DMA_TO_DEVICE);
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- }
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-
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- drv_data->dma_mapped = 0;
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-}
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-
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-static int wait_ssp_rx_stall(struct driver_data *drv_data)
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-{
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- unsigned long limit = loops_per_jiffy << 1;
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-
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- while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit)
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- cpu_relax();
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-
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- return limit;
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-}
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-
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-static int wait_dma_channel_stop(int channel)
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-{
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- unsigned long limit = loops_per_jiffy << 1;
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-
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- while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
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- cpu_relax();
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-
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- return limit;
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-}
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-
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-static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
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- const char *msg)
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-{
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- /* Stop and reset */
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- DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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- DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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- write_SSSR_CS(drv_data, drv_data->clear_sr);
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- pxa2xx_spi_write(drv_data, SSCR1,
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- pxa2xx_spi_read(drv_data, SSCR1)
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- & ~drv_data->dma_cr1);
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- if (!pxa25x_ssp_comp(drv_data))
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- pxa2xx_spi_write(drv_data, SSTO, 0);
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- pxa2xx_spi_flush(drv_data);
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- pxa2xx_spi_write(drv_data, SSCR0,
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- pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
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-
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- pxa2xx_spi_unmap_dma_buffers(drv_data);
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-
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- dev_err(&drv_data->pdev->dev, "%s\n", msg);
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-
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- drv_data->cur_msg->state = ERROR_STATE;
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- tasklet_schedule(&drv_data->pump_transfers);
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-}
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-
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-static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
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-{
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- struct spi_message *msg = drv_data->cur_msg;
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-
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- /* Clear and disable interrupts on SSP and DMA channels*/
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- pxa2xx_spi_write(drv_data, SSCR1,
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- pxa2xx_spi_read(drv_data, SSCR1)
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- & ~drv_data->dma_cr1);
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- write_SSSR_CS(drv_data, drv_data->clear_sr);
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- DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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- DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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-
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- if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
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- dev_err(&drv_data->pdev->dev,
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- "dma_handler: dma rx channel stop failed\n");
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-
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- if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
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- dev_err(&drv_data->pdev->dev,
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- "dma_transfer: ssp rx stall failed\n");
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-
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- pxa2xx_spi_unmap_dma_buffers(drv_data);
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-
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- /* update the buffer pointer for the amount completed in dma */
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- drv_data->rx += drv_data->len -
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- (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
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-
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- /* read trailing data from fifo, it does not matter how many
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- * bytes are in the fifo just read until buffer is full
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- * or fifo is empty, which ever occurs first */
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- drv_data->read(drv_data);
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-
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- /* return count of what was actually read */
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- msg->actual_length += drv_data->len -
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- (drv_data->rx_end - drv_data->rx);
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-
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- /* Transfer delays and chip select release are
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- * handled in pump_transfers or giveback
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- */
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-
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- /* Move to next transfer */
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- msg->state = pxa2xx_spi_next_transfer(drv_data);
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-
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- /* Schedule transfer tasklet */
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- tasklet_schedule(&drv_data->pump_transfers);
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-}
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-
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-void pxa2xx_spi_dma_handler(int channel, void *data)
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-{
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- struct driver_data *drv_data = data;
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- u32 irq_status = DCSR(channel) & DMA_INT_MASK;
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-
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- if (irq_status & DCSR_BUSERR) {
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-
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- if (channel == drv_data->tx_channel)
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- pxa2xx_spi_dma_error_stop(drv_data,
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- "dma_handler: bad bus address on tx channel");
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- else
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- pxa2xx_spi_dma_error_stop(drv_data,
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- "dma_handler: bad bus address on rx channel");
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- return;
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- }
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-
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- /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
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- if ((channel == drv_data->tx_channel)
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- && (irq_status & DCSR_ENDINTR)
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- && (drv_data->ssp_type == PXA25x_SSP)) {
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-
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- /* Wait for rx to stall */
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- if (wait_ssp_rx_stall(drv_data) == 0)
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- dev_err(&drv_data->pdev->dev,
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- "dma_handler: ssp rx stall failed\n");
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-
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- /* finish this transfer, start the next */
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- pxa2xx_spi_dma_transfer_complete(drv_data);
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- }
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-}
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-
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-irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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-{
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- u32 irq_status;
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-
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- irq_status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
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- if (irq_status & SSSR_ROR) {
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- pxa2xx_spi_dma_error_stop(drv_data,
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- "dma_transfer: fifo overrun");
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- return IRQ_HANDLED;
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- }
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-
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- /* Check for false positive timeout */
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- if ((irq_status & SSSR_TINT)
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- && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
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- pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
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- return IRQ_HANDLED;
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- }
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-
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- if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
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-
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- /* Clear and disable timeout interrupt, do the rest in
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- * dma_transfer_complete */
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- if (!pxa25x_ssp_comp(drv_data))
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- pxa2xx_spi_write(drv_data, SSTO, 0);
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-
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- /* finish this transfer, start the next */
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- pxa2xx_spi_dma_transfer_complete(drv_data);
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-
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- return IRQ_HANDLED;
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- }
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-
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- /* Opps problem detected */
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- return IRQ_NONE;
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-}
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-
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-int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
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-{
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- u32 dma_width;
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-
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- switch (drv_data->n_bytes) {
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- case 1:
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- dma_width = DCMD_WIDTH1;
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- break;
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- case 2:
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- dma_width = DCMD_WIDTH2;
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- break;
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- default:
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- dma_width = DCMD_WIDTH4;
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- break;
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- }
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-
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- /* Setup rx DMA Channel */
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- DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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- DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
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- DTADR(drv_data->rx_channel) = drv_data->rx_dma;
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- if (drv_data->rx == drv_data->null_dma_buf)
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- /* No target address increment */
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- DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
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- | dma_width
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- | dma_burst
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- | drv_data->len;
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- else
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- DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
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- | DCMD_FLOWSRC
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- | dma_width
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- | dma_burst
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- | drv_data->len;
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-
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- /* Setup tx DMA Channel */
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- DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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- DSADR(drv_data->tx_channel) = drv_data->tx_dma;
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- DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
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- if (drv_data->tx == drv_data->null_dma_buf)
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- /* No source address increment */
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- DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
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- | dma_width
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- | dma_burst
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- | drv_data->len;
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- else
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- DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
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- | DCMD_FLOWTRG
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- | dma_width
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- | dma_burst
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- | drv_data->len;
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-
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- /* Enable dma end irqs on SSP to detect end of transfer */
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- if (drv_data->ssp_type == PXA25x_SSP)
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- DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
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-
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- return 0;
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-}
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-
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-void pxa2xx_spi_dma_start(struct driver_data *drv_data)
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-{
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- DCSR(drv_data->rx_channel) |= DCSR_RUN;
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- DCSR(drv_data->tx_channel) |= DCSR_RUN;
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-}
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-
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-int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
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-{
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- struct device *dev = &drv_data->pdev->dev;
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- struct ssp_device *ssp = drv_data->ssp;
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-
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- /* Get two DMA channels (rx and tx) */
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- drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
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- DMA_PRIO_HIGH,
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- pxa2xx_spi_dma_handler,
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- drv_data);
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- if (drv_data->rx_channel < 0) {
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- dev_err(dev, "problem (%d) requesting rx channel\n",
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- drv_data->rx_channel);
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- return -ENODEV;
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- }
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- drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
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- DMA_PRIO_MEDIUM,
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- pxa2xx_spi_dma_handler,
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- drv_data);
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- if (drv_data->tx_channel < 0) {
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- dev_err(dev, "problem (%d) requesting tx channel\n",
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- drv_data->tx_channel);
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- pxa_free_dma(drv_data->rx_channel);
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- return -ENODEV;
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- }
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-
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- DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
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- DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
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-
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- return 0;
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-}
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-
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-void pxa2xx_spi_dma_release(struct driver_data *drv_data)
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-{
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- struct ssp_device *ssp = drv_data->ssp;
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-
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- DRCMR(ssp->drcmr_rx) = 0;
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- DRCMR(ssp->drcmr_tx) = 0;
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-
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- if (drv_data->tx_channel != 0)
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- pxa_free_dma(drv_data->tx_channel);
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- if (drv_data->rx_channel != 0)
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- pxa_free_dma(drv_data->rx_channel);
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-}
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-
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-void pxa2xx_spi_dma_resume(struct driver_data *drv_data)
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-{
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- if (drv_data->rx_channel != -1)
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- DRCMR(drv_data->ssp->drcmr_rx) =
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- DRCMR_MAPVLD | drv_data->rx_channel;
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- if (drv_data->tx_channel != -1)
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- DRCMR(drv_data->ssp->drcmr_tx) =
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- DRCMR_MAPVLD | drv_data->tx_channel;
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-}
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-
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-int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
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- struct spi_device *spi,
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- u8 bits_per_word, u32 *burst_code,
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- u32 *threshold)
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|
-{
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- struct pxa2xx_spi_chip *chip_info =
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- (struct pxa2xx_spi_chip *)spi->controller_data;
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- int bytes_per_word;
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- int burst_bytes;
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- int thresh_words;
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- int req_burst_size;
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- int retval = 0;
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-
|
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- /* Set the threshold (in registers) to equal the same amount of data
|
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|
- * as represented by burst size (in bytes). The computation below
|
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- * is (burst_size rounded up to nearest 8 byte, word or long word)
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- * divided by (bytes/register); the tx threshold is the inverse of
|
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- * the rx, so that there will always be enough data in the rx fifo
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- * to satisfy a burst, and there will always be enough space in the
|
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- * tx fifo to accept a burst (a tx burst will overwrite the fifo if
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- * there is not enough space), there must always remain enough empty
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- * space in the rx fifo for any data loaded to the tx fifo.
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- * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
|
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- * will be 8, or half the fifo;
|
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- * The threshold can only be set to 2, 4 or 8, but not 16, because
|
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- * to burst 16 to the tx fifo, the fifo would have to be empty;
|
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- * however, the minimum fifo trigger level is 1, and the tx will
|
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- * request service when the fifo is at this level, with only 15 spaces.
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- */
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-
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- /* find bytes/word */
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- if (bits_per_word <= 8)
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- bytes_per_word = 1;
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- else if (bits_per_word <= 16)
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- bytes_per_word = 2;
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- else
|
|
|
- bytes_per_word = 4;
|
|
|
-
|
|
|
- /* use struct pxa2xx_spi_chip->dma_burst_size if available */
|
|
|
- if (chip_info)
|
|
|
- req_burst_size = chip_info->dma_burst_size;
|
|
|
- else {
|
|
|
- switch (chip->dma_burst_size) {
|
|
|
- default:
|
|
|
- /* if the default burst size is not set,
|
|
|
- * do it now */
|
|
|
- chip->dma_burst_size = DCMD_BURST8;
|
|
|
- case DCMD_BURST8:
|
|
|
- req_burst_size = 8;
|
|
|
- break;
|
|
|
- case DCMD_BURST16:
|
|
|
- req_burst_size = 16;
|
|
|
- break;
|
|
|
- case DCMD_BURST32:
|
|
|
- req_burst_size = 32;
|
|
|
- break;
|
|
|
- }
|
|
|
- }
|
|
|
- if (req_burst_size <= 8) {
|
|
|
- *burst_code = DCMD_BURST8;
|
|
|
- burst_bytes = 8;
|
|
|
- } else if (req_burst_size <= 16) {
|
|
|
- if (bytes_per_word == 1) {
|
|
|
- /* don't burst more than 1/2 the fifo */
|
|
|
- *burst_code = DCMD_BURST8;
|
|
|
- burst_bytes = 8;
|
|
|
- retval = 1;
|
|
|
- } else {
|
|
|
- *burst_code = DCMD_BURST16;
|
|
|
- burst_bytes = 16;
|
|
|
- }
|
|
|
- } else {
|
|
|
- if (bytes_per_word == 1) {
|
|
|
- /* don't burst more than 1/2 the fifo */
|
|
|
- *burst_code = DCMD_BURST8;
|
|
|
- burst_bytes = 8;
|
|
|
- retval = 1;
|
|
|
- } else if (bytes_per_word == 2) {
|
|
|
- /* don't burst more than 1/2 the fifo */
|
|
|
- *burst_code = DCMD_BURST16;
|
|
|
- burst_bytes = 16;
|
|
|
- retval = 1;
|
|
|
- } else {
|
|
|
- *burst_code = DCMD_BURST32;
|
|
|
- burst_bytes = 32;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- thresh_words = burst_bytes / bytes_per_word;
|
|
|
-
|
|
|
- /* thresh_words will be between 2 and 8 */
|
|
|
- *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
|
|
|
- | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
|
|
|
-
|
|
|
- return retval;
|
|
|
-}
|
Mark Brown
10 years ago