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@@ -890,10 +890,6 @@ static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
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static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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{
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- u32 srbm_gfx_cntl = 0;
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- u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
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- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
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-
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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if (vm_id < 8) {
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@@ -903,40 +899,6 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
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}
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amdgpu_ring_write(ring, pd_addr >> 12);
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- /* update SH_MEM_* regs */
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- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
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- amdgpu_ring_write(ring, srbm_gfx_cntl);
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-
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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- amdgpu_ring_write(ring, mmSH_MEM_BASES);
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- amdgpu_ring_write(ring, 0);
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-
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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- amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
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- amdgpu_ring_write(ring, sh_mem_cfg);
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-
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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- amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
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- amdgpu_ring_write(ring, 1);
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-
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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- amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
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- amdgpu_ring_write(ring, 0);
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-
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- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
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- amdgpu_ring_write(ring, srbm_gfx_cntl);
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-
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-
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/* flush TLB */
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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