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@@ -213,12 +213,17 @@ static void mei_me_hw_config(struct mei_device *dev)
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hcsr = mei_hcsr_read(dev);
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dev->hbuf_depth = (hcsr & H_CBD) >> 24;
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- hw->pg_state = MEI_PG_OFF;
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-
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reg = 0;
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pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
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hw->d0i3_supported =
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((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
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+
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+ hw->pg_state = MEI_PG_OFF;
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+ if (hw->d0i3_supported) {
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+ reg = mei_me_d0i3c_read(dev);
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+ if (reg & H_D0I3C_I3)
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+ hw->pg_state = MEI_PG_ON;
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+ }
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}
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/**
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@@ -1037,12 +1042,24 @@ int mei_me_pg_exit_sync(struct mei_device *dev)
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* @dev: the device structure
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* @intr_enable: if interrupt should be enabled after reset.
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*
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- * Return: always 0
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+ * Return: 0 on success an error code otherwise
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*/
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static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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{
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- u32 hcsr = mei_hcsr_read(dev);
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+ struct mei_me_hw *hw = to_me_hw(dev);
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+ int ret;
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+ u32 hcsr;
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+
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+ if (intr_enable) {
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+ mei_me_intr_enable(dev);
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+ if (hw->d0i3_supported) {
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+ ret = mei_me_d0i3_exit_sync(dev);
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+ if (ret)
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+ return ret;
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+ }
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+ }
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+ hcsr = mei_hcsr_read(dev);
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/* H_RST may be found lit before reset is started,
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* for example if preceding reset flow hasn't completed.
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* In that case asserting H_RST will be ignored, therefore
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@@ -1057,9 +1074,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
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- if (intr_enable)
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- hcsr |= H_CSR_IE_MASK;
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- else
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+ if (!intr_enable)
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hcsr &= ~H_CSR_IE_MASK;
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dev->recvd_hw_ready = false;
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@@ -1077,9 +1092,14 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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if ((hcsr & H_RDY) == H_RDY)
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dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
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- if (intr_enable == false)
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+ if (!intr_enable) {
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mei_me_hw_reset_release(dev);
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-
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+ if (hw->d0i3_supported) {
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+ ret = mei_me_d0i3_enter(dev);
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+ if (ret)
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+ return ret;
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+ }
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+ }
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return 0;
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}
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