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@@ -46,8 +46,8 @@
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#define R8A7790_CLK_MSIOF1 8
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#define R8A7790_CLK_MSIOF1 8
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#define R8A7790_CLK_MSIOF3 15
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#define R8A7790_CLK_MSIOF3 15
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#define R8A7790_CLK_SCIFB2 16
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#define R8A7790_CLK_SCIFB2 16
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-#define R8A7790_CLK_SYS_DMAC0 18
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-#define R8A7790_CLK_SYS_DMAC1 19
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+#define R8A7790_CLK_SYS_DMAC1 18
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+#define R8A7790_CLK_SYS_DMAC0 19
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/* MSTP3 */
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/* MSTP3 */
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#define R8A7790_CLK_TPU0 4
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#define R8A7790_CLK_TPU0 4
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