|
@@ -2466,12 +2466,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
|
|
|
if (IS_G4X(dev))
|
|
|
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
|
|
|
|
|
|
- linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
|
|
|
+ linear_offset = y * fb->pitches[0] + x * pixel_size;
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
|
intel_crtc->dspaddr_offset =
|
|
|
intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
|
|
|
- fb->bits_per_pixel / 8,
|
|
|
+ pixel_size,
|
|
|
fb->pitches[0]);
|
|
|
linear_offset -= intel_crtc->dspaddr_offset;
|
|
|
} else {
|
|
@@ -2574,10 +2574,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
|
|
|
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
|
|
|
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
|
|
|
|
|
|
- linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
|
|
|
+ linear_offset = y * fb->pitches[0] + x * pixel_size;
|
|
|
intel_crtc->dspaddr_offset =
|
|
|
intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
|
|
|
- fb->bits_per_pixel / 8,
|
|
|
+ pixel_size,
|
|
|
fb->pitches[0]);
|
|
|
linear_offset -= intel_crtc->dspaddr_offset;
|
|
|
if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
|