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@@ -143,9 +143,9 @@
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/* FLEXCAN interrupt flag register (IFLAG) bits */
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/* FLEXCAN interrupt flag register (IFLAG) bits */
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/* Errata ERR005829 step7: Reserve first valid MB */
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/* Errata ERR005829 step7: Reserve first valid MB */
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-#define FLEXCAN_TX_BUF_RESERVED 8
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-#define FLEXCAN_TX_BUF_ID 9
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-#define FLEXCAN_IFLAG_BUF(x) BIT(x)
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+#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
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+#define FLEXCAN_TX_MB_OFF_FIFO 9
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+#define FLEXCAN_IFLAG_MB(x) BIT(x)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
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#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
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@@ -256,6 +256,9 @@ struct flexcan_priv {
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struct napi_struct napi;
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struct napi_struct napi;
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struct flexcan_regs __iomem *regs;
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struct flexcan_regs __iomem *regs;
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+ struct flexcan_mb __iomem *tx_mb;
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+ struct flexcan_mb __iomem *tx_mb_reserved;
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+ u8 tx_mb_idx;
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u32 reg_esr;
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u32 reg_esr;
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u32 reg_ctrl_default;
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u32 reg_ctrl_default;
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u32 reg_imask1_default;
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u32 reg_imask1_default;
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@@ -472,7 +475,6 @@ static int flexcan_get_berr_counter(const struct net_device *dev,
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static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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{
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const struct flexcan_priv *priv = netdev_priv(dev);
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const struct flexcan_priv *priv = netdev_priv(dev);
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- struct flexcan_regs __iomem *regs = priv->regs;
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struct can_frame *cf = (struct can_frame *)skb->data;
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struct can_frame *cf = (struct can_frame *)skb->data;
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u32 can_id;
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u32 can_id;
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u32 data;
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u32 data;
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@@ -495,25 +497,25 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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if (cf->can_dlc > 0) {
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if (cf->can_dlc > 0) {
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data = be32_to_cpup((__be32 *)&cf->data[0]);
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data = be32_to_cpup((__be32 *)&cf->data[0]);
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- flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[0]);
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+ flexcan_write(data, &priv->tx_mb->data[0]);
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}
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}
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if (cf->can_dlc > 3) {
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if (cf->can_dlc > 3) {
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data = be32_to_cpup((__be32 *)&cf->data[4]);
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data = be32_to_cpup((__be32 *)&cf->data[4]);
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- flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[1]);
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+ flexcan_write(data, &priv->tx_mb->data[1]);
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}
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}
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can_put_echo_skb(skb, dev, 0);
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can_put_echo_skb(skb, dev, 0);
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- flexcan_write(can_id, ®s->mb[FLEXCAN_TX_BUF_ID].can_id);
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- flexcan_write(ctrl, ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
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+ flexcan_write(can_id, &priv->tx_mb->can_id);
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+ flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
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/* Errata ERR005829 step8:
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/* Errata ERR005829 step8:
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* Write twice INACTIVE(0x8) code to first MB.
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* Write twice INACTIVE(0x8) code to first MB.
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*/
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*/
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
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+ &priv->tx_mb_reserved->can_ctrl);
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
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+ &priv->tx_mb_reserved->can_ctrl);
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return NETDEV_TX_OK;
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return NETDEV_TX_OK;
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}
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}
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@@ -750,7 +752,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
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}
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}
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/* transmission complete interrupt */
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/* transmission complete interrupt */
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- if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
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+ if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
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handled = IRQ_HANDLED;
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handled = IRQ_HANDLED;
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stats->tx_bytes += can_get_echo_skb(dev, 0);
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stats->tx_bytes += can_get_echo_skb(dev, 0);
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stats->tx_packets++;
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stats->tx_packets++;
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@@ -758,8 +760,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
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/* after sending a RTR frame MB is in RX mode */
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/* after sending a RTR frame MB is in RX mode */
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
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- flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
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+ &priv->tx_mb->can_ctrl);
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+ flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
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netif_wake_queue(dev);
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netif_wake_queue(dev);
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}
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}
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@@ -849,7 +851,7 @@ static int flexcan_chip_start(struct net_device *dev)
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reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
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reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
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reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
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reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
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FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
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FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
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- FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
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+ FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
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netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
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netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
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flexcan_write(reg_mcr, ®s->mcr);
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flexcan_write(reg_mcr, ®s->mcr);
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@@ -887,18 +889,18 @@ static int flexcan_chip_start(struct net_device *dev)
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flexcan_write(reg_ctrl, ®s->ctrl);
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flexcan_write(reg_ctrl, ®s->ctrl);
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/* clear and invalidate all mailboxes first */
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/* clear and invalidate all mailboxes first */
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- for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
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+ for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
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flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
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flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
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®s->mb[i].can_ctrl);
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®s->mb[i].can_ctrl);
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}
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}
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/* Errata ERR005829: mark first TX mailbox as INACTIVE */
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/* Errata ERR005829: mark first TX mailbox as INACTIVE */
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
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+ &priv->tx_mb_reserved->can_ctrl);
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/* mark TX mailbox as INACTIVE */
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/* mark TX mailbox as INACTIVE */
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
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+ &priv->tx_mb->can_ctrl);
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/* acceptance mask/acceptance code (accept everything) */
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/* acceptance mask/acceptance code (accept everything) */
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flexcan_write(0x0, ®s->rxgmask);
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flexcan_write(0x0, ®s->rxgmask);
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@@ -1229,9 +1231,13 @@ static int flexcan_probe(struct platform_device *pdev)
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priv->devtype_data = devtype_data;
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priv->devtype_data = devtype_data;
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priv->reg_xceiver = reg_xceiver;
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priv->reg_xceiver = reg_xceiver;
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+ priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
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+ priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
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+ priv->tx_mb = ®s->mb[priv->tx_mb_idx];
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+
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priv->reg_imask1_default = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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priv->reg_imask1_default = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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FLEXCAN_IFLAG_RX_FIFO_AVAILABLE |
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FLEXCAN_IFLAG_RX_FIFO_AVAILABLE |
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- FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID);
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+ FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
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netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
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