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@@ -36,6 +36,7 @@
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#define GPC_PGC_SW_SHIFT 0x0
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#define IMR_NUM 4
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+#define GPC_MAX_IRQS (IMR_NUM * 32)
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#define GPU_VPU_PUP_REQ BIT(1)
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#define GPU_VPU_PDN_REQ BIT(0)
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@@ -99,17 +100,17 @@ void imx_gpc_post_resume(void)
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static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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- unsigned int idx = d->hwirq / 32 - 1;
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+ unsigned int idx = d->hwirq / 32;
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u32 mask;
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- /* Sanity check for SPI irq */
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- if (d->hwirq < 32)
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- return -EINVAL;
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-
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mask = 1 << d->hwirq % 32;
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gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
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gpc_wake_irqs[idx] & ~mask;
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+ /*
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+ * Do *not* call into the parent, as the GIC doesn't have any
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+ * wake-up facility...
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+ */
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return 0;
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}
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@@ -139,7 +140,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
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void __iomem *reg;
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u32 val;
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- reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
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+ reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << hwirq % 32);
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writel_relaxed(val, reg);
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@@ -150,7 +151,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
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void __iomem *reg;
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u32 val;
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- reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
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+ reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val |= 1 << (hwirq % 32);
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writel_relaxed(val, reg);
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@@ -158,41 +159,119 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
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static void imx_gpc_irq_unmask(struct irq_data *d)
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{
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- /* Sanity check for SPI irq */
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- if (d->hwirq < 32)
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- return;
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-
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imx_gpc_hwirq_unmask(d->hwirq);
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+ irq_chip_unmask_parent(d);
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}
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static void imx_gpc_irq_mask(struct irq_data *d)
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{
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- /* Sanity check for SPI irq */
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- if (d->hwirq < 32)
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- return;
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-
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imx_gpc_hwirq_mask(d->hwirq);
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+ irq_chip_mask_parent(d);
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}
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-void __init imx_gpc_init(void)
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+static struct irq_chip imx_gpc_chip = {
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+ .name = "GPC",
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+ .irq_eoi = irq_chip_eoi_parent,
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+ .irq_mask = imx_gpc_irq_mask,
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+ .irq_unmask = imx_gpc_irq_unmask,
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+ .irq_retrigger = irq_chip_retrigger_hierarchy,
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+ .irq_set_wake = imx_gpc_irq_set_wake,
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+};
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+
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+static int imx_gpc_domain_xlate(struct irq_domain *domain,
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+ struct device_node *controller,
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+ const u32 *intspec,
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+ unsigned int intsize,
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+ unsigned long *out_hwirq,
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+ unsigned int *out_type)
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{
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- struct device_node *np;
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+ if (domain->of_node != controller)
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+ return -EINVAL; /* Shouldn't happen, really... */
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+ if (intsize != 3)
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+ return -EINVAL; /* Not GIC compliant */
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+ if (intspec[0] != 0)
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+ return -EINVAL; /* No PPI should point to this domain */
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+
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+ *out_hwirq = intspec[1];
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+ *out_type = intspec[2];
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+ return 0;
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+}
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+
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+static int imx_gpc_domain_alloc(struct irq_domain *domain,
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+ unsigned int irq,
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+ unsigned int nr_irqs, void *data)
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+{
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+ struct of_phandle_args *args = data;
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+ struct of_phandle_args parent_args;
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+ irq_hw_number_t hwirq;
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int i;
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- np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
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- gpc_base = of_iomap(np, 0);
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- WARN_ON(!gpc_base);
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+ if (args->args_count != 3)
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+ return -EINVAL; /* Not GIC compliant */
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+ if (args->args[0] != 0)
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+ return -EINVAL; /* No PPI should point to this domain */
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+
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+ hwirq = args->args[1];
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+ if (hwirq >= GPC_MAX_IRQS)
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+ return -EINVAL; /* Can't deal with this */
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+
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+ for (i = 0; i < nr_irqs; i++)
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+ irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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+ &imx_gpc_chip, NULL);
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+
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+ parent_args = *args;
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+ parent_args.np = domain->parent->of_node;
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+ return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
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+}
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+
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+static struct irq_domain_ops imx_gpc_domain_ops = {
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+ .xlate = imx_gpc_domain_xlate,
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+ .alloc = imx_gpc_domain_alloc,
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+ .free = irq_domain_free_irqs_common,
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+};
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+
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+static int __init imx_gpc_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ struct irq_domain *parent_domain, *domain;
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+ int i;
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+
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+ if (!parent) {
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+ pr_err("%s: no parent, giving up\n", node->full_name);
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+ return -ENODEV;
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+ }
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+
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+ parent_domain = irq_find_host(parent);
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+ if (!parent_domain) {
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+ pr_err("%s: unable to obtain parent domain\n", node->full_name);
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+ return -ENXIO;
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+ }
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+
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+ gpc_base = of_iomap(node, 0);
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+ if (WARN_ON(!gpc_base))
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+ return -ENOMEM;
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+
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+ domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
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+ node, &imx_gpc_domain_ops,
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+ NULL);
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+ if (!domain) {
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+ iounmap(gpc_base);
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+ return -ENOMEM;
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+ }
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/* Initially mask all interrupts */
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
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- /* Register GPC as the secondary interrupt controller behind GIC */
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- gic_arch_extn.irq_mask = imx_gpc_irq_mask;
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- gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
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- gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
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+ return 0;
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}
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+/*
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+ * We cannot use the IRQCHIP_DECLARE macro that lives in
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+ * drivers/irqchip, so we're forced to roll our own. Not very nice.
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+ */
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+OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
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+
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#ifdef CONFIG_PM_GENERIC_DOMAINS
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static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
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Marc Zyngier