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@@ -388,6 +388,84 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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return 0;
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return 0;
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}
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}
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+
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+static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
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+ enum pci_bus_speed *speed,
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+ enum pcie_link_width *width)
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+{
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+ u32 lnkcap1, lnkcap2;
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+ int err1, err2;
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+
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+#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
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+
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+ *speed = PCI_SPEED_UNKNOWN;
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+ *width = PCIE_LNK_WIDTH_UNKNOWN;
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+
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+ err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
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+ err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
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+ if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
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+ if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
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+ *speed = PCIE_SPEED_8_0GT;
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+ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
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+ *speed = PCIE_SPEED_5_0GT;
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+ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
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+ *speed = PCIE_SPEED_2_5GT;
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+ }
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+ if (!err1) {
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+ *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
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+ if (!lnkcap2) { /* pre-r3.0 */
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+ if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
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+ *speed = PCIE_SPEED_5_0GT;
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+ else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
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+ *speed = PCIE_SPEED_2_5GT;
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+ }
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+ }
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+
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+ if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
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+ return err1 ? err1 :
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+ err2 ? err2 : -EINVAL;
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+ }
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+ return 0;
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+}
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+
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+static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
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+{
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+ enum pcie_link_width width, width_cap;
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+ enum pci_bus_speed speed, speed_cap;
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+ int err;
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+
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+#define PCIE_SPEED_STR(speed) \
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+ (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
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+ speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
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+ speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
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+ "Unknown")
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+
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+ err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
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+ if (err) {
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+ mlx4_warn(dev,
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+ "Unable to determine PCIe device BW capabilities\n");
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+ return;
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+ }
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+
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+ err = pcie_get_minimum_link(dev->pdev, &speed, &width);
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+ if (err || speed == PCI_SPEED_UNKNOWN ||
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+ width == PCIE_LNK_WIDTH_UNKNOWN) {
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+ mlx4_warn(dev,
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+ "Unable to determine PCI device chain minimum BW\n");
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+ return;
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+ }
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+
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+ if (width != width_cap || speed != speed_cap)
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+ mlx4_warn(dev,
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+ "PCIe BW is different than device's capability\n");
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+
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+ mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
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+ PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
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+ mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
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+ width, width_cap);
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+ return;
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+}
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+
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/*The function checks if there are live vf, return the num of them*/
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/*The function checks if there are live vf, return the num of them*/
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static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
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static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
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{
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{
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@@ -2306,6 +2384,12 @@ slave_start:
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goto err_mfunc;
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goto err_mfunc;
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}
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}
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+ /* check if the device is functioning at its maximum possible speed.
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+ * No return code for this call, just warn the user in case of PCI
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+ * express device capabilities are under-satisfied by the bus.
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+ */
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+ mlx4_check_pcie_caps(dev);
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+
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/* In master functions, the communication channel must be initialized
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/* In master functions, the communication channel must be initialized
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* after obtaining its address from fw */
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* after obtaining its address from fw */
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if (mlx4_is_master(dev)) {
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if (mlx4_is_master(dev)) {
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