drm/nouveau/gr: rename from graph (no binary change)

Shorter device name, match Tegra and our existing enums.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvif/class.h

@@ -122,7 +122,7 @@ struct nv_device_v0 {
 #define NV_DEVICE_V0_DISABLE_CORE                         0x0000000000000008ULL
 #define NV_DEVICE_V0_DISABLE_DISP                         0x0000000000010000ULL
 #define NV_DEVICE_V0_DISABLE_FIFO                         0x0000000000020000ULL
-#define NV_DEVICE_V0_DISABLE_GRAPH                        0x0000000100000000ULL
+#define NV_DEVICE_V0_DISABLE_GR                           0x0000000100000000ULL
 #define NV_DEVICE_V0_DISABLE_MPEG                         0x0000000200000000ULL
 #define NV_DEVICE_V0_DISABLE_ME                           0x0000000400000000ULL
 #define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL

drivers/gpu/drm/nouveau/include/nvif/device.h

@@ -52,11 +52,11 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
 
 #include <engine/device.h>
 #include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/software.h>
 
 #define nvkm_fifo(a) nouveau_fifo(nvkm_device(a))
 #define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a))
-#define nvkm_gr(a) ((struct nouveau_graph *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
+#define nvkm_gr(a) ((struct nouveau_gr *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
 
 #endif

drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h

@@ -0,0 +1,86 @@
+#ifndef __NOUVEAU_GR_H__
+#define __NOUVEAU_GR_H__
+
+#include <core/engine.h>
+#include <core/engctx.h>
+#include <core/enum.h>
+
+struct nouveau_gr_chan {
+	struct nouveau_engctx base;
+};
+
+#define nouveau_gr_context_create(p,e,c,g,s,a,f,d)                          \
+	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nouveau_gr_context_destroy(d)                                       \
+	nouveau_engctx_destroy(&(d)->base)
+#define nouveau_gr_context_init(d)                                          \
+	nouveau_engctx_init(&(d)->base)
+#define nouveau_gr_context_fini(d,s)                                        \
+	nouveau_engctx_fini(&(d)->base, (s))
+
+#define _nouveau_gr_context_dtor _nouveau_engctx_dtor
+#define _nouveau_gr_context_init _nouveau_engctx_init
+#define _nouveau_gr_context_fini _nouveau_engctx_fini
+#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32
+#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32
+
+struct nouveau_gr {
+	struct nouveau_engine base;
+
+	/* Returns chipset-specific counts of units packed into an u64.
+	 */
+	u64 (*units)(struct nouveau_gr *);
+};
+
+static inline struct nouveau_gr *
+nouveau_gr(void *obj)
+{
+	return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
+}
+
+#define nouveau_gr_create(p,e,c,y,d)                                        \
+	nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
+#define nouveau_gr_destroy(d)                                               \
+	nouveau_engine_destroy(&(d)->base)
+#define nouveau_gr_init(d)                                                  \
+	nouveau_engine_init(&(d)->base)
+#define nouveau_gr_fini(d,s)                                                \
+	nouveau_engine_fini(&(d)->base, (s))
+
+#define _nouveau_gr_dtor _nouveau_engine_dtor
+#define _nouveau_gr_init _nouveau_engine_init
+#define _nouveau_gr_fini _nouveau_engine_fini
+
+extern struct nouveau_oclass nv04_gr_oclass;
+extern struct nouveau_oclass nv10_gr_oclass;
+extern struct nouveau_oclass nv20_gr_oclass;
+extern struct nouveau_oclass nv25_gr_oclass;
+extern struct nouveau_oclass nv2a_gr_oclass;
+extern struct nouveau_oclass nv30_gr_oclass;
+extern struct nouveau_oclass nv34_gr_oclass;
+extern struct nouveau_oclass nv35_gr_oclass;
+extern struct nouveau_oclass nv40_gr_oclass;
+extern struct nouveau_oclass nv50_gr_oclass;
+extern struct nouveau_oclass *nvc0_gr_oclass;
+extern struct nouveau_oclass *nvc1_gr_oclass;
+extern struct nouveau_oclass *nvc4_gr_oclass;
+extern struct nouveau_oclass *nvc8_gr_oclass;
+extern struct nouveau_oclass *nvd7_gr_oclass;
+extern struct nouveau_oclass *nvd9_gr_oclass;
+extern struct nouveau_oclass *nve4_gr_oclass;
+extern struct nouveau_oclass *gk20a_gr_oclass;
+extern struct nouveau_oclass *nvf0_gr_oclass;
+extern struct nouveau_oclass *gk110b_gr_oclass;
+extern struct nouveau_oclass *nv108_gr_oclass;
+extern struct nouveau_oclass *gm107_gr_oclass;
+
+extern const struct nouveau_bitfield nv04_gr_nsource[];
+extern struct nouveau_ofuncs nv04_gr_ofuncs;
+bool nv04_gr_idle(void *obj);
+
+extern const struct nouveau_bitfield nv10_gr_intr_name[];
+extern const struct nouveau_bitfield nv10_gr_nstatus[];
+
+extern const struct nouveau_enum nv50_data_error_names[];
+
+#endif

drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h

@@ -1,86 +0,0 @@
-#ifndef __NOUVEAU_GRAPH_H__
-#define __NOUVEAU_GRAPH_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-struct nouveau_graph_chan {
-	struct nouveau_engctx base;
-};
-
-#define nouveau_graph_context_create(p,e,c,g,s,a,f,d)                          \
-	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_graph_context_destroy(d)                                       \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_graph_context_init(d)                                          \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_graph_context_fini(d,s)                                        \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_graph_context_dtor _nouveau_engctx_dtor
-#define _nouveau_graph_context_init _nouveau_engctx_init
-#define _nouveau_graph_context_fini _nouveau_engctx_fini
-#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32
-
-struct nouveau_graph {
-	struct nouveau_engine base;
-
-	/* Returns chipset-specific counts of units packed into an u64.
-	 */
-	u64 (*units)(struct nouveau_graph *);
-};
-
-static inline struct nouveau_graph *
-nouveau_graph(void *obj)
-{
-	return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
-}
-
-#define nouveau_graph_create(p,e,c,y,d)                                        \
-	nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
-#define nouveau_graph_destroy(d)                                               \
-	nouveau_engine_destroy(&(d)->base)
-#define nouveau_graph_init(d)                                                  \
-	nouveau_engine_init(&(d)->base)
-#define nouveau_graph_fini(d,s)                                                \
-	nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_graph_dtor _nouveau_engine_dtor
-#define _nouveau_graph_init _nouveau_engine_init
-#define _nouveau_graph_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass nv04_graph_oclass;
-extern struct nouveau_oclass nv10_graph_oclass;
-extern struct nouveau_oclass nv20_graph_oclass;
-extern struct nouveau_oclass nv25_graph_oclass;
-extern struct nouveau_oclass nv2a_graph_oclass;
-extern struct nouveau_oclass nv30_graph_oclass;
-extern struct nouveau_oclass nv34_graph_oclass;
-extern struct nouveau_oclass nv35_graph_oclass;
-extern struct nouveau_oclass nv40_graph_oclass;
-extern struct nouveau_oclass nv50_graph_oclass;
-extern struct nouveau_oclass *nvc0_graph_oclass;
-extern struct nouveau_oclass *nvc1_graph_oclass;
-extern struct nouveau_oclass *nvc4_graph_oclass;
-extern struct nouveau_oclass *nvc8_graph_oclass;
-extern struct nouveau_oclass *nvd7_graph_oclass;
-extern struct nouveau_oclass *nvd9_graph_oclass;
-extern struct nouveau_oclass *nve4_graph_oclass;
-extern struct nouveau_oclass *gk20a_graph_oclass;
-extern struct nouveau_oclass *nvf0_graph_oclass;
-extern struct nouveau_oclass *gk110b_graph_oclass;
-extern struct nouveau_oclass *nv108_graph_oclass;
-extern struct nouveau_oclass *gm107_graph_oclass;
-
-extern const struct nouveau_bitfield nv04_graph_nsource[];
-extern struct nouveau_ofuncs nv04_graph_ofuncs;
-bool nv04_graph_idle(void *obj);
-
-extern const struct nouveau_bitfield nv10_graph_intr_name[];
-extern const struct nouveau_bitfield nv10_graph_nstatus[];
-
-extern const struct nouveau_enum nv50_data_error_names[];
-
-#endif

drivers/gpu/drm/nouveau/nouveau_abi16.c

@@ -165,7 +165,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nvif_device *device = &drm->device;
 	struct nouveau_timer *ptimer = nvkm_timer(device);
-	struct nouveau_graph *graph = nvkm_gr(device);
+	struct nouveau_gr *gr = nvkm_gr(device);
 	struct drm_nouveau_getparam *getparam = data;
 
 	switch (getparam->param) {
@@ -215,7 +215,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
 		getparam->value = 1;
 		break;
 	case NOUVEAU_GETPARAM_GRAPH_UNITS:
-		getparam->value = graph->units ? graph->units(graph) : 0;
+		getparam->value = gr->units ? gr->units(gr) : 0;
 		break;
 	default:
 		NV_PRINTK(debug, cli, "unknown parameter %lld\n", getparam->param);

drivers/gpu/drm/nouveau/nvkm/engine/Kbuild

@@ -8,7 +8,7 @@ include $(src)/nvkm/engine/device/Kbuild
 include $(src)/nvkm/engine/disp/Kbuild
 include $(src)/nvkm/engine/dmaobj/Kbuild
 include $(src)/nvkm/engine/fifo/Kbuild
-include $(src)/nvkm/engine/graph/Kbuild
+include $(src)/nvkm/engine/gr/Kbuild
 include $(src)/nvkm/engine/mpeg/Kbuild
 include $(src)/nvkm/engine/msvld/Kbuild
 include $(src)/nvkm/engine/perfmon/Kbuild

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -228,7 +228,7 @@ static const u64 disable_map[] = {
 	[NVDEV_ENGINE_PERFMON]  = NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_ENGINE_FIFO]	= NV_DEVICE_V0_DISABLE_FIFO,
 	[NVDEV_ENGINE_SW]	= NV_DEVICE_V0_DISABLE_FIFO,
-	[NVDEV_ENGINE_GR]	= NV_DEVICE_V0_DISABLE_GRAPH,
+	[NVDEV_ENGINE_GR]	= NV_DEVICE_V0_DISABLE_GR,
 	[NVDEV_ENGINE_MPEG]	= NV_DEVICE_V0_DISABLE_MPEG,
 	[NVDEV_ENGINE_ME]	= NV_DEVICE_V0_DISABLE_ME,
 	[NVDEV_ENGINE_VP]	= NV_DEVICE_V0_DISABLE_VP,

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

@@ -46,7 +46,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 #include <engine/ce.h>
 #include <engine/bsp.h>
@@ -86,7 +86,7 @@ gm100_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 #if 0
@@ -130,7 +130,7 @@ gm100_identify(struct nouveau_device *device)
 #if 0
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 #endif
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
 #if 0

drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c

@@ -37,7 +37,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 
 int
@@ -59,7 +59,7 @@ nv04_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x05:
@@ -77,7 +77,7 @@ nv04_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c

@@ -38,7 +38,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 
 int
@@ -59,7 +59,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
 		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x15:
@@ -78,7 +78,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x16:
@@ -97,7 +97,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x1a:
@@ -116,7 +116,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x11:
@@ -135,7 +135,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x17:
@@ -154,7 +154,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x1f:
@@ -173,7 +173,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x18:
@@ -192,7 +192,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c

@@ -39,7 +39,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 
 int
@@ -62,7 +62,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x25:
@@ -81,7 +81,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x28:
@@ -100,7 +100,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x2a:
@@ -119,7 +119,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c

@@ -38,7 +38,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/mpeg.h>
 #include <engine/disp.h>
 
@@ -62,7 +62,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x35:
@@ -81,7 +81,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x31:
@@ -100,7 +100,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
@@ -120,7 +120,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
@@ -140,7 +140,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c

@@ -41,7 +41,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/mpeg.h>
 #include <engine/disp.h>
 #include <engine/perfmon.h>
@@ -68,7 +68,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -91,7 +91,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -114,7 +114,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -137,7 +137,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -160,7 +160,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -183,7 +183,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -206,7 +206,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -229,7 +229,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -252,7 +252,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -275,7 +275,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -298,7 +298,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -321,7 +321,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -344,7 +344,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -367,7 +367,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -390,7 +390,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -413,7 +413,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

@@ -44,7 +44,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/mpeg.h>
 #include <engine/vp.h>
 #include <engine/cipher.h>
@@ -81,7 +81,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv50_perfmon_oclass;
@@ -107,7 +107,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -136,7 +136,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -165,7 +165,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -194,7 +194,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -223,7 +223,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -252,7 +252,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -281,7 +281,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -310,7 +310,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -339,7 +339,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -369,7 +369,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -400,7 +400,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
@@ -430,7 +430,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
@@ -460,7 +460,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

@@ -46,7 +46,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/vp.h>
 #include <engine/bsp.h>
 #include <engine/msvld.h>
@@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c

@@ -46,7 +46,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 #include <engine/ce.h>
 #include <engine/bsp.h>
@@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -177,7 +177,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_gr_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &gk20a_volt_oclass;
@@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -241,7 +241,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild

@@ -0,0 +1,36 @@
+nvkm-y += nvkm/engine/gr/ctxnv40.o
+nvkm-y += nvkm/engine/gr/ctxnv50.o
+nvkm-y += nvkm/engine/gr/ctxnvc0.o
+nvkm-y += nvkm/engine/gr/ctxnvc1.o
+nvkm-y += nvkm/engine/gr/ctxnvc4.o
+nvkm-y += nvkm/engine/gr/ctxnvc8.o
+nvkm-y += nvkm/engine/gr/ctxnvd7.o
+nvkm-y += nvkm/engine/gr/ctxnvd9.o
+nvkm-y += nvkm/engine/gr/ctxnve4.o
+nvkm-y += nvkm/engine/gr/ctxgk20a.o
+nvkm-y += nvkm/engine/gr/ctxnvf0.o
+nvkm-y += nvkm/engine/gr/ctxgk110b.o
+nvkm-y += nvkm/engine/gr/ctxnv108.o
+nvkm-y += nvkm/engine/gr/ctxgm107.o
+nvkm-y += nvkm/engine/gr/nv04.o
+nvkm-y += nvkm/engine/gr/nv10.o
+nvkm-y += nvkm/engine/gr/nv20.o
+nvkm-y += nvkm/engine/gr/nv25.o
+nvkm-y += nvkm/engine/gr/nv2a.o
+nvkm-y += nvkm/engine/gr/nv30.o
+nvkm-y += nvkm/engine/gr/nv34.o
+nvkm-y += nvkm/engine/gr/nv35.o
+nvkm-y += nvkm/engine/gr/nv40.o
+nvkm-y += nvkm/engine/gr/nv50.o
+nvkm-y += nvkm/engine/gr/nvc0.o
+nvkm-y += nvkm/engine/gr/nvc1.o
+nvkm-y += nvkm/engine/gr/nvc4.o
+nvkm-y += nvkm/engine/gr/nvc8.o
+nvkm-y += nvkm/engine/gr/nvd7.o
+nvkm-y += nvkm/engine/gr/nvd9.o
+nvkm-y += nvkm/engine/gr/nve4.o
+nvkm-y += nvkm/engine/gr/gk20a.o
+nvkm-y += nvkm/engine/gr/nvf0.o
+nvkm-y += nvkm/engine/gr/gk110b.o
+nvkm-y += nvkm/engine/gr/nv108.o
+nvkm-y += nvkm/engine/gr/gm107.o

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gk110b_grctx_init_sm_0[] = {
 	{ 0x419e04,   1, 0x04, 0x00000000 },
 	{ 0x419e08,   1, 0x04, 0x0000001d },
@@ -56,7 +56,7 @@ gk110b_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gk110b_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nvf0_grctx_init_tex_0 },
@@ -74,12 +74,12 @@ struct nouveau_oclass *
 gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xf1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c

@@ -22,7 +22,7 @@
 
 #include "ctxnvc0.h"
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gk20a_grctx_pack_mthd[] = {
 	{ nve4_grctx_init_a097_0, 0xa297 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
@@ -33,12 +33,12 @@ struct nouveau_oclass *
 gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xea),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -287,13 +287,13 @@ gm107_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_icmd[] = {
 	{ gm107_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_b097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -610,14 +610,14 @@ gm107_grctx_init_b097_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_mthd[] = {
 	{ gm107_grctx_init_b097_0, 0xb097 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_fe_0[] = {
 	{ 0x404004,   8, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -639,7 +639,7 @@ gm107_grctx_init_fe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8001bf },
 	{ 0x405830,   1, 0x04, 0x0aa01000 },
@@ -653,7 +653,7 @@ gm107_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x07410001 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -669,7 +669,7 @@ gm107_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x32802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -682,7 +682,7 @@ gm107_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ gm107_grctx_init_fe_0 },
@@ -697,13 +697,13 @@ gm107_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_gpc_unk_0[] = {
 	{ 0x418380,   1, 0x04, 0x00000056 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000007f },
 	{ 0x418684,   1, 0x04, 0x0000001f },
@@ -714,7 +714,7 @@ gm107_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006863a },
 	{ 0x418810,   1, 0x04, 0x00000000 },
@@ -727,7 +727,7 @@ gm107_grctx_init_setup_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_gpc_unk_2[] = {
 	{ 0x418d24,   1, 0x04, 0x00000000 },
 	{ 0x418e00,   1, 0x04, 0x90000000 },
@@ -741,7 +741,7 @@ gm107_grctx_init_gpc_unk_2[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_gpc[] = {
 	{ gm107_grctx_init_gpc_unk_0 },
 	{ nv108_grctx_init_prop_0 },
@@ -755,7 +755,7 @@ gm107_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000300f0 },
 	{ 0x419a04,   1, 0x04, 0x00000005 },
@@ -771,7 +771,7 @@ gm107_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000001a },
 	{ 0x419c04,   1, 0x04, 0x80000006 },
@@ -785,13 +785,13 @@ gm107_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_l1c_0[] = {
 	{ 0x419c84,   1, 0x04, 0x00000020 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00001c02 },
@@ -812,7 +812,7 @@ gm107_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ gm107_grctx_init_tex_0 },
@@ -822,7 +822,7 @@ gm107_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x00000000 },
 	{ 0x41bec4,   1, 0x04, 0x01050000 },
@@ -832,7 +832,7 @@ gm107_grctx_init_cbm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_wwdx_0[] = {
 	{ 0x41bf00,   1, 0x04, 0x0a418820 },
 	{ 0x41bf04,   1, 0x04, 0x062080e6 },
@@ -846,7 +846,7 @@ gm107_grctx_init_wwdx_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ gm107_grctx_init_cbm_0 },
@@ -893,7 +893,7 @@ gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
 static void
 gm107_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);
 	const u32  alpha = impl->alpha_nr;
 	const u32 attrib = impl->attrib_nr;
@@ -930,7 +930,7 @@ gm107_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 static void
-gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
+gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
 {
 	int gpc, tpc, id;
 
@@ -950,16 +950,16 @@ gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
 }
 
 static void
-gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -988,9 +988,9 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 		nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
 	}
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 
 	nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
 	nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
@@ -1002,12 +1002,12 @@ struct nouveau_oclass *
 gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0x08),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = gm107_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -278,13 +278,13 @@ nv108_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_icmd[] = {
 	{ nv108_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_fe_0[] = {
 	{ 0x404004,   8, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -311,7 +311,7 @@ nv108_grctx_init_fe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180648 },
@@ -325,7 +325,7 @@ nv108_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x034103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -340,7 +340,7 @@ nv108_grctx_init_pd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nv108_grctx_init_rstr2d_0[] = {
 	{ 0x407804,   1, 0x04, 0x00000063 },
 	{ 0x40780c,   1, 0x04, 0x0a418820 },
@@ -353,7 +353,7 @@ nv108_grctx_init_rstr2d_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x32802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -366,7 +366,7 @@ nv108_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nv108_grctx_init_fe_0 },
@@ -381,7 +381,7 @@ nv108_grctx_pack_hub[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nv108_grctx_init_prop_0[] = {
 	{ 0x418400,   1, 0x04, 0x38005e00 },
 	{ 0x418404,   1, 0x04, 0x71e0ffff },
@@ -394,7 +394,7 @@ nv108_grctx_init_prop_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000007f },
 	{ 0x418684,   1, 0x04, 0x0000001f },
@@ -404,7 +404,7 @@ nv108_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006863a },
 	{ 0x418808,   1, 0x04, 0x00000000 },
@@ -419,7 +419,7 @@ nv108_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nv108_grctx_init_crstr_0[] = {
 	{ 0x418b00,   1, 0x04, 0x0000001e },
 	{ 0x418b08,   1, 0x04, 0x0a418820 },
@@ -432,7 +432,7 @@ nv108_grctx_init_crstr_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -443,7 +443,7 @@ nv108_grctx_init_gpm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nv108_grctx_init_prop_0 },
@@ -457,7 +457,7 @@ nv108_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000100f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -472,7 +472,7 @@ nv108_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_sm_0[] = {
 	{ 0x419e04,   1, 0x04, 0x00000000 },
 	{ 0x419e08,   1, 0x04, 0x0000001d },
@@ -500,7 +500,7 @@ nv108_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nv108_grctx_init_tex_0 },
@@ -510,7 +510,7 @@ nv108_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x10000000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
@@ -519,7 +519,7 @@ nv108_grctx_init_cbm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ nv108_grctx_init_cbm_0 },
@@ -535,12 +535,12 @@ struct nouveau_oclass *
 nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0x08),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

@@ -119,7 +119,7 @@
  */
 
 static int
-nv40_graph_vs_count(struct nouveau_device *device)
+nv40_gr_vs_count(struct nouveau_device *device)
 {
 
 	switch (device->chipset) {
@@ -158,7 +158,7 @@ enum cp_label {
 };
 
 static void
-nv40_graph_construct_general(struct nouveau_grctx *ctx)
+nv40_gr_construct_general(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -208,7 +208,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
 		gr_def(ctx, 0x4009dc, 0x80000000);
 	} else {
 		cp_ctx(ctx, 0x400840, 20);
-		if (nv44_graph_class(ctx->device)) {
+		if (nv44_gr_class(ctx->device)) {
 			for (i = 0; i < 8; i++)
 				gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
 		}
@@ -217,7 +217,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
 		gr_def(ctx, 0x400888, 0x00000040);
 		cp_ctx(ctx, 0x400894, 11);
 		gr_def(ctx, 0x400894, 0x00000040);
-		if (!nv44_graph_class(ctx->device)) {
+		if (!nv44_gr_class(ctx->device)) {
 			for (i = 0; i < 8; i++)
 				gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
 		}
@@ -264,7 +264,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -369,7 +369,7 @@ nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -504,8 +504,8 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
 
 	cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);
 	cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);
-	cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device));
-	for (i = 0; i < nv40_graph_vs_count(ctx->device); i++)
+	cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device));
+	for (i = 0; i < nv40_gr_vs_count(ctx->device); i++)
 		gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
 
 	if (device->chipset != 0x40) {
@@ -533,9 +533,9 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
 {
-	int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684;
+	int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
 
 	cp_out (ctx, 0x300000);
 	cp_lsr (ctx, len - 4);
@@ -548,14 +548,14 @@ nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_shader(struct nouveau_grctx *ctx)
+nv40_gr_construct_shader(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	struct nouveau_gpuobj *obj = ctx->data;
 	int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
 	int offset, i;
 
-	vs_nr    = nv40_graph_vs_count(ctx->device);
+	vs_nr    = nv40_gr_vs_count(ctx->device);
 	vs_nr_b0 = 363;
 	vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;
 	if (device->chipset == 0x40) {
@@ -570,11 +570,11 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx)
 	} else {
 		b0_offset = 0x1d40/4; /* 2200 */
 		b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
-		vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4;
+		vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4;
 	}
 
 	cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
-	cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041);
+	cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041);
 
 	offset = ctx->ctxvals_pos;
 	ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
@@ -629,23 +629,23 @@ nv40_grctx_generate(struct nouveau_grctx *ctx)
 	/* general PGRAPH state */
 	cp_name(ctx, cp_swap_state);
 	cp_pos (ctx, 0x00020/4);
-	nv40_graph_construct_general(ctx);
+	nv40_gr_construct_general(ctx);
 	cp_wait(ctx, STATUS, IDLE);
 
 	/* 3D state, block 1 */
 	cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
-	nv40_graph_construct_state3d(ctx);
+	nv40_gr_construct_state3d(ctx);
 	cp_wait(ctx, STATUS, IDLE);
 
 	/* 3D state, block 2 */
-	nv40_graph_construct_state3d_2(ctx);
+	nv40_gr_construct_state3d_2(ctx);
 
 	/* Some other block of "random" state */
-	nv40_graph_construct_state3d_3(ctx);
+	nv40_gr_construct_state3d_3(ctx);
 
 	/* Per-vertex shader state */
 	cp_pos (ctx, ctx->ctxvals_pos);
-	nv40_graph_construct_shader(ctx);
+	nv40_gr_construct_shader(ctx);
 
 	/* pre-exit state updates */
 	cp_name(ctx, cp_prepare_exit);

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

@@ -169,9 +169,9 @@ enum cp_label {
 	cp_exit,
 };
 
-static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_mmio(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_xfer1(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_xfer2(struct nouveau_grctx *ctx);
 
 /* Main function: construct the ctxprog skeleton, call the other functions. */
 
@@ -219,9 +219,9 @@ nv50_grctx_generate(struct nouveau_grctx *ctx)
 	cp_pos (ctx, 0x00004/4);
 	cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
 	cp_pos (ctx, 0x00100/4);
-	nv50_graph_construct_mmio(ctx);
-	nv50_graph_construct_xfer1(ctx);
-	nv50_graph_construct_xfer2(ctx);
+	nv50_gr_construct_mmio(ctx);
+	nv50_gr_construct_xfer1(ctx);
+	nv50_gr_construct_xfer2(ctx);
 
 	cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
 
@@ -293,10 +293,10 @@ nv50_grctx_init(struct nouveau_device *device, u32 *size)
  */
 
 static void
-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx);
+nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx);
 
 static void
-nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i, j;
@@ -334,7 +334,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
 		gr_def(ctx, 0x400b20, 0x0001629d);
 	}
 
-	nv50_graph_construct_mmio_ddata(ctx);
+	nv50_gr_construct_mmio_ddata(ctx);
 
 	/* 0C00: VFETCH */
 	cp_ctx(ctx, 0x400c08, 0x2);
@@ -793,7 +793,7 @@ dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
 }
 
 static void
-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int base, num;
@@ -1166,27 +1166,27 @@ xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
 
 /* Gene declarations... */
 
-static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx);
 
 static void
-nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer1(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -1200,32 +1200,32 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 	if (device->chipset < 0xa0) {
 		/* Strand 0 */
 		ctx->ctxvals_pos = offset;
-		nv50_graph_construct_gene_dispatch(ctx);
-		nv50_graph_construct_gene_m2mf(ctx);
-		nv50_graph_construct_gene_unk24xx(ctx);
-		nv50_graph_construct_gene_clipid(ctx);
-		nv50_graph_construct_gene_zcull(ctx);
+		nv50_gr_construct_gene_dispatch(ctx);
+		nv50_gr_construct_gene_m2mf(ctx);
+		nv50_gr_construct_gene_unk24xx(ctx);
+		nv50_gr_construct_gene_clipid(ctx);
+		nv50_gr_construct_gene_zcull(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 1 */
 		ctx->ctxvals_pos = offset + 0x1;
-		nv50_graph_construct_gene_vfetch(ctx);
-		nv50_graph_construct_gene_eng2d(ctx);
-		nv50_graph_construct_gene_csched(ctx);
-		nv50_graph_construct_gene_ropm1(ctx);
-		nv50_graph_construct_gene_ropm2(ctx);
+		nv50_gr_construct_gene_vfetch(ctx);
+		nv50_gr_construct_gene_eng2d(ctx);
+		nv50_gr_construct_gene_csched(ctx);
+		nv50_gr_construct_gene_ropm1(ctx);
+		nv50_gr_construct_gene_ropm2(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 2 */
 		ctx->ctxvals_pos = offset + 0x2;
-		nv50_graph_construct_gene_ccache(ctx);
-		nv50_graph_construct_gene_unk1cxx(ctx);
-		nv50_graph_construct_gene_strmout(ctx);
-		nv50_graph_construct_gene_unk14xx(ctx);
-		nv50_graph_construct_gene_unk10xx(ctx);
-		nv50_graph_construct_gene_unk34xx(ctx);
+		nv50_gr_construct_gene_ccache(ctx);
+		nv50_gr_construct_gene_unk1cxx(ctx);
+		nv50_gr_construct_gene_strmout(ctx);
+		nv50_gr_construct_gene_unk14xx(ctx);
+		nv50_gr_construct_gene_unk10xx(ctx);
+		nv50_gr_construct_gene_unk34xx(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
@@ -1233,7 +1233,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 		ctx->ctxvals_pos = offset + 3;
 		for (i = 0; i < 6; i++)
 			if (units & (1 << (i + 16)))
-				nv50_graph_construct_gene_ropc(ctx);
+				nv50_gr_construct_gene_ropc(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
@@ -1241,74 +1241,74 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 		for (i = 0; i < 4; i++) {
 			ctx->ctxvals_pos = offset + 4 + i;
 			if (units & (1 << (2 * i)))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if (units & (1 << (2 * i + 1)))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if ((ctx->ctxvals_pos-offset)/8 > size)
 				size = (ctx->ctxvals_pos-offset)/8;
 		}
 	} else {
 		/* Strand 0 */
 		ctx->ctxvals_pos = offset;
-		nv50_graph_construct_gene_dispatch(ctx);
-		nv50_graph_construct_gene_m2mf(ctx);
-		nv50_graph_construct_gene_unk34xx(ctx);
-		nv50_graph_construct_gene_csched(ctx);
-		nv50_graph_construct_gene_unk1cxx(ctx);
-		nv50_graph_construct_gene_strmout(ctx);
+		nv50_gr_construct_gene_dispatch(ctx);
+		nv50_gr_construct_gene_m2mf(ctx);
+		nv50_gr_construct_gene_unk34xx(ctx);
+		nv50_gr_construct_gene_csched(ctx);
+		nv50_gr_construct_gene_unk1cxx(ctx);
+		nv50_gr_construct_gene_strmout(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 1 */
 		ctx->ctxvals_pos = offset + 1;
-		nv50_graph_construct_gene_unk10xx(ctx);
+		nv50_gr_construct_gene_unk10xx(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 2 */
 		ctx->ctxvals_pos = offset + 2;
 		if (device->chipset == 0xa0)
-			nv50_graph_construct_gene_unk14xx(ctx);
-		nv50_graph_construct_gene_unk24xx(ctx);
+			nv50_gr_construct_gene_unk14xx(ctx);
+		nv50_gr_construct_gene_unk24xx(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 3 */
 		ctx->ctxvals_pos = offset + 3;
-		nv50_graph_construct_gene_vfetch(ctx);
+		nv50_gr_construct_gene_vfetch(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 4 */
 		ctx->ctxvals_pos = offset + 4;
-		nv50_graph_construct_gene_ccache(ctx);
+		nv50_gr_construct_gene_ccache(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 5 */
 		ctx->ctxvals_pos = offset + 5;
-		nv50_graph_construct_gene_ropm2(ctx);
-		nv50_graph_construct_gene_ropm1(ctx);
+		nv50_gr_construct_gene_ropm2(ctx);
+		nv50_gr_construct_gene_ropm1(ctx);
 		/* per-ROP context */
 		for (i = 0; i < 8; i++)
 			if (units & (1<<(i+16)))
-				nv50_graph_construct_gene_ropc(ctx);
+				nv50_gr_construct_gene_ropc(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 6 */
 		ctx->ctxvals_pos = offset + 6;
-		nv50_graph_construct_gene_zcull(ctx);
-		nv50_graph_construct_gene_clipid(ctx);
-		nv50_graph_construct_gene_eng2d(ctx);
+		nv50_gr_construct_gene_zcull(ctx);
+		nv50_gr_construct_gene_clipid(ctx);
+		nv50_gr_construct_gene_eng2d(ctx);
 		if (units & (1 << 0))
-			nv50_graph_construct_xfer_tp(ctx);
+			nv50_gr_construct_xfer_tp(ctx);
 		if (units & (1 << 1))
-			nv50_graph_construct_xfer_tp(ctx);
+			nv50_gr_construct_xfer_tp(ctx);
 		if (units & (1 << 2))
-			nv50_graph_construct_xfer_tp(ctx);
+			nv50_gr_construct_xfer_tp(ctx);
 		if (units & (1 << 3))
-			nv50_graph_construct_xfer_tp(ctx);
+			nv50_gr_construct_xfer_tp(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
@@ -1316,19 +1316,19 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 		ctx->ctxvals_pos = offset + 7;
 		if (device->chipset == 0xa0) {
 			if (units & (1 << 4))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if (units & (1 << 5))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if (units & (1 << 6))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if (units & (1 << 7))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if (units & (1 << 8))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 			if (units & (1 << 9))
-				nv50_graph_construct_xfer_tp(ctx);
+				nv50_gr_construct_xfer_tp(ctx);
 		} else {
-			nv50_graph_construct_gene_unk14xx(ctx);
+			nv50_gr_construct_gene_unk14xx(ctx);
 		}
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
@@ -1349,7 +1349,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
  */
 
 static void
-nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx)
 {
 	/* start of strand 0 */
 	struct nouveau_device *device = ctx->device;
@@ -1405,7 +1405,7 @@ nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx)
 {
 	/* Strand 0, right after dispatch */
 	struct nouveau_device *device = ctx->device;
@@ -1457,7 +1457,7 @@ nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	xf_emit(ctx, 2, 0);		/* RO */
@@ -1525,7 +1525,7 @@ nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -1585,7 +1585,7 @@ nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	/* end of area 2 on pre-NVA0, area 1 on NVAx */
@@ -1610,7 +1610,7 @@ nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	/* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
@@ -1721,7 +1721,7 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
@@ -1782,7 +1782,7 @@ nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx)
 {
 	/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
 	/* SEEK */
@@ -1802,7 +1802,7 @@ nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -1885,7 +1885,7 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int acnt = 0x10, rep, i;
@@ -2071,7 +2071,7 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	/* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
@@ -2133,7 +2133,7 @@ nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
@@ -2232,7 +2232,7 @@ nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */
@@ -2328,7 +2328,7 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	xf_emit(ctx, 1, 0x102);		/* 0000ffff STRMOUT_BUFFER_CTRL */
@@ -2370,7 +2370,7 @@ nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0D64 */
@@ -2383,7 +2383,7 @@ nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	/* SEEK */
@@ -2409,7 +2409,7 @@ nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int magic2;
@@ -2644,7 +2644,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int magic3;
@@ -2736,7 +2736,7 @@ nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int magic1, magic2;
@@ -3036,7 +3036,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	xf_emit(ctx, 2, 0);		/* 1 LINKED_TSC. yes, 2. */
@@ -3082,7 +3082,7 @@ nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */
@@ -3121,24 +3121,24 @@ nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	if (device->chipset < 0xa0) {
-		nv50_graph_construct_xfer_unk84xx(ctx);
-		nv50_graph_construct_xfer_tprop(ctx);
-		nv50_graph_construct_xfer_tex(ctx);
-		nv50_graph_construct_xfer_unk8cxx(ctx);
+		nv50_gr_construct_xfer_unk84xx(ctx);
+		nv50_gr_construct_xfer_tprop(ctx);
+		nv50_gr_construct_xfer_tex(ctx);
+		nv50_gr_construct_xfer_unk8cxx(ctx);
 	} else {
-		nv50_graph_construct_xfer_tex(ctx);
-		nv50_graph_construct_xfer_tprop(ctx);
-		nv50_graph_construct_xfer_unk8cxx(ctx);
-		nv50_graph_construct_xfer_unk84xx(ctx);
+		nv50_gr_construct_xfer_tex(ctx);
+		nv50_gr_construct_xfer_tprop(ctx);
+		nv50_gr_construct_xfer_unk8cxx(ctx);
+		nv50_gr_construct_xfer_unk84xx(ctx);
 	}
 }
 
 static void
-nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i, mpcnt = 2;
@@ -3270,7 +3270,7 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
 }
 
 static void
-nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer2(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -3288,7 +3288,7 @@ nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
 			if (i == 0)
 				xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
 			if (units & (1 << i))
-				nv50_graph_construct_xfer_mpc(ctx);
+				nv50_gr_construct_xfer_mpc(ctx);
 			if ((ctx->ctxvals_pos-offset)/8 > size)
 				size = (ctx->ctxvals_pos-offset)/8;
 		}
@@ -3299,40 +3299,40 @@ nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
 		 * what it's doing here. */
 		xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
 		if (units & (1 << 0))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if (units & (1 << 1))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 1: TPs 2, 3 */
 		ctx->ctxvals_pos = offset + 1;
 		if (units & (1 << 2))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if (units & (1 << 3))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 2: TPs 4, 5, 6 */
 		ctx->ctxvals_pos = offset + 2;
 		if (units & (1 << 4))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if (units & (1 << 5))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if (units & (1 << 6))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 
 		/* Strand 3: TPs 7, 8, 9 */
 		ctx->ctxvals_pos = offset + 3;
 		if (units & (1 << 7))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if (units & (1 << 8))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if (units & (1 << 9))
-			nv50_graph_construct_xfer_mpc(ctx);
+			nv50_gr_construct_xfer_mpc(ctx);
 		if ((ctx->ctxvals_pos-offset)/8 > size)
 			size = (ctx->ctxvals_pos-offset)/8;
 	}

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -266,13 +266,13 @@ nvc0_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvc0_grctx_pack_icmd[] = {
 	{ nvc0_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_9097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -575,7 +575,7 @@ nvc0_grctx_init_9097_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_902d_0[] = {
 	{ 0x000200,   1, 0x04, 0x000000cf },
 	{ 0x000204,   1, 0x04, 0x00000001 },
@@ -594,7 +594,7 @@ nvc0_grctx_init_902d_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_9039_0[] = {
 	{ 0x00030c,   3, 0x04, 0x00000000 },
 	{ 0x000320,   1, 0x04, 0x00000000 },
@@ -603,7 +603,7 @@ nvc0_grctx_init_9039_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_90c0_0[] = {
 	{ 0x00270c,   8, 0x20, 0x00000000 },
 	{ 0x00030c,   1, 0x04, 0x00000001 },
@@ -621,7 +621,7 @@ nvc0_grctx_init_90c0_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvc0_grctx_pack_mthd[] = {
 	{ nvc0_grctx_init_9097_0, 0x9097 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
@@ -630,13 +630,13 @@ nvc0_grctx_pack_mthd[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_main_0[] = {
 	{ 0x400204,   2, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_fe_0[] = {
 	{ 0x404004,  11, 0x04, 0x00000000 },
 	{ 0x404044,   1, 0x04, 0x00000000 },
@@ -657,7 +657,7 @@ nvc0_grctx_init_fe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_pri_0[] = {
 	{ 0x404404,  14, 0x04, 0x00000000 },
 	{ 0x404460,   2, 0x04, 0x00000000 },
@@ -668,7 +668,7 @@ nvc0_grctx_init_pri_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_memfmt_0[] = {
 	{ 0x404604,   1, 0x04, 0x00000015 },
 	{ 0x404608,   1, 0x04, 0x00000000 },
@@ -690,7 +690,7 @@ nvc0_grctx_init_memfmt_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x078000bf },
 	{ 0x405830,   1, 0x04, 0x02180000 },
@@ -702,7 +702,7 @@ nvc0_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -712,7 +712,7 @@ nvc0_grctx_init_pd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_rstr2d_0[] = {
 	{ 0x407804,   1, 0x04, 0x00000023 },
 	{ 0x40780c,   1, 0x04, 0x0a418820 },
@@ -725,7 +725,7 @@ nvc0_grctx_init_rstr2d_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_scc_0[] = {
 	{ 0x408000,   2, 0x04, 0x00000000 },
 	{ 0x408008,   1, 0x04, 0x00000018 },
@@ -736,7 +736,7 @@ nvc0_grctx_init_scc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -748,7 +748,7 @@ nvc0_grctx_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvc0_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvc0_grctx_init_fe_0 },
@@ -762,13 +762,13 @@ nvc0_grctx_pack_hub[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_gpc_unk_0[] = {
 	{ 0x418380,   1, 0x04, 0x00000016 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_prop_0[] = {
 	{ 0x418400,   1, 0x04, 0x38004e00 },
 	{ 0x418404,   1, 0x04, 0x71e0ffff },
@@ -782,7 +782,7 @@ nvc0_grctx_init_prop_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000001f },
 	{ 0x418684,   1, 0x04, 0x0000000f },
@@ -794,7 +794,7 @@ nvc0_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x0006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -807,7 +807,7 @@ nvc0_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_zcull_0[] = {
 	{ 0x41891c,   1, 0x04, 0x00ff00ff },
 	{ 0x418924,   1, 0x04, 0x00000000 },
@@ -816,7 +816,7 @@ nvc0_grctx_init_zcull_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_crstr_0[] = {
 	{ 0x418b00,   1, 0x04, 0x00000000 },
 	{ 0x418b08,   1, 0x04, 0x0a418820 },
@@ -829,7 +829,7 @@ nvc0_grctx_init_crstr_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -838,7 +838,7 @@ nvc0_grctx_init_gpm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_gcc_0[] = {
 	{ 0x419000,   1, 0x04, 0x00000780 },
 	{ 0x419004,   2, 0x04, 0x00000000 },
@@ -846,7 +846,7 @@ nvc0_grctx_init_gcc_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvc0_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvc0_grctx_init_prop_0 },
@@ -859,7 +859,7 @@ nvc0_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_zcullr_0[] = {
 	{ 0x418a00,   3, 0x04, 0x00000000 },
 	{ 0x418a0c,   1, 0x04, 0x00010000 },
@@ -888,13 +888,13 @@ nvc0_grctx_init_zcullr_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvc0_grctx_pack_zcull[] = {
 	{ nvc0_grctx_init_zcullr_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_pe_0[] = {
 	{ 0x419818,   1, 0x04, 0x00000000 },
 	{ 0x41983c,   1, 0x04, 0x00038bc7 },
@@ -904,7 +904,7 @@ nvc0_grctx_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -915,7 +915,7 @@ nvc0_grctx_init_tex_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_wwdx_0[] = {
 	{ 0x419b00,   1, 0x04, 0x0a418820 },
 	{ 0x419b04,   1, 0x04, 0x062080e6 },
@@ -929,7 +929,7 @@ nvc0_grctx_init_wwdx_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x00000002 },
 	{ 0x419c04,   1, 0x04, 0x00000006 },
@@ -938,7 +938,7 @@ nvc0_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_l1c_0[] = {
 	{ 0x419cb0,   1, 0x04, 0x00060048 },
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
@@ -946,14 +946,14 @@ nvc0_grctx_init_l1c_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc0_grctx_init_tpccs_0[] = {
 	{ 0x419d20,   1, 0x04, 0x02180000 },
 	{ 0x419d24,   1, 0x04, 0x00001fff },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc0_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000002 },
@@ -966,7 +966,7 @@ nvc0_grctx_init_sm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvc0_grctx_pack_tpc[] = {
 	{ nvc0_grctx_init_pe_0 },
 	{ nvc0_grctx_init_tex_0 },
@@ -1049,7 +1049,7 @@ nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
 void
 nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
 	const u32 attrib = impl->attrib_nr;
 	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -1074,12 +1074,12 @@ nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 void
-nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_unkn(struct nvc0_gr_priv *priv)
 {
 }
 
 void
-nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
 {
 	int gpc, tpc, id;
 
@@ -1100,7 +1100,7 @@ nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
 }
 
 void
-nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r406028(struct nvc0_gr_priv *priv)
 {
 	u32 tmp[GPC_MAX / 8] = {}, i = 0;
 	for (i = 0; i < priv->gpc_nr; i++)
@@ -1112,7 +1112,7 @@ nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
 }
 
 void
-nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *priv)
 {
 	u8  tpcnr[GPC_MAX], data[TPC_MAX];
 	int gpc, tpc, i;
@@ -1134,7 +1134,7 @@ nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
 }
 
 void
-nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
 {
 	u32 data[6] = {}, data2[2] = {};
 	u8  tpcnr[GPC_MAX];
@@ -1192,7 +1192,7 @@ nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
 }
 
 void
-nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r406800(struct nvc0_gr_priv *priv)
 {
 	u64 tpc_mask = 0, tpc_set = 0;
 	u8  tpcnr[GPC_MAX];
@@ -1225,17 +1225,17 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
 }
 
 void
-nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nvc0_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -1250,14 +1250,14 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 	nvc0_grctx_generate_r418bb8(priv);
 	nvc0_grctx_generate_r406800(priv);
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 }
 
 int
-nvc0_grctx_generate(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate(struct nvc0_gr_priv *priv)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	struct nouveau_bar *bar = nouveau_bar(priv);
@@ -1361,12 +1361,12 @@ struct nouveau_oclass *
 nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc0),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc0_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h

@@ -0,0 +1,202 @@
+#ifndef __NVKM_GRCTX_NVC0_H__
+#define __NVKM_GRCTX_NVC0_H__
+
+#include "nvc0.h"
+
+struct nvc0_grctx {
+	struct nvc0_gr_priv *priv;
+	struct nvc0_gr_data *data;
+	struct nvc0_gr_mmio *mmio;
+	int buffer_nr;
+	u64 buffer[4];
+	u64 addr;
+};
+
+int  nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
+void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
+
+#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
+#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
+#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
+#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c),  0, -1)
+
+struct nvc0_grctx_oclass {
+	struct nouveau_oclass base;
+	/* main context generation function */
+	void  (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *);
+	/* context-specific modify-on-first-load list generation function */
+	void  (*unkn)(struct nvc0_gr_priv *);
+	/* mmio context data */
+	const struct nvc0_gr_pack *hub;
+	const struct nvc0_gr_pack *gpc;
+	const struct nvc0_gr_pack *zcull;
+	const struct nvc0_gr_pack *tpc;
+	const struct nvc0_gr_pack *ppc;
+	/* indirect context data, generated with icmds/mthds */
+	const struct nvc0_gr_pack *icmd;
+	const struct nvc0_gr_pack *mthd;
+	/* bundle circular buffer */
+	void (*bundle)(struct nvc0_grctx *);
+	u32 bundle_size;
+	u32 bundle_min_gpm_fifo_depth;
+	u32 bundle_token_limit;
+	/* pagepool */
+	void (*pagepool)(struct nvc0_grctx *);
+	u32 pagepool_size;
+	/* attribute(/alpha) circular buffer */
+	void (*attrib)(struct nvc0_grctx *);
+	u32 attrib_nr_max;
+	u32 attrib_nr;
+	u32 alpha_nr_max;
+	u32 alpha_nr;
+};
+
+static inline const struct nvc0_grctx_oclass *
+nvc0_grctx_impl(struct nvc0_gr_priv *priv)
+{
+	return (void *)nv_engine(priv)->cclass;
+}
+
+extern struct nouveau_oclass *nvc0_grctx_oclass;
+int  nvc0_grctx_generate(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
+void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
+void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
+void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
+void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvc1_grctx_oclass;
+void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
+void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvc4_grctx_oclass;
+extern struct nouveau_oclass *nvc8_grctx_oclass;
+
+extern struct nouveau_oclass *nvd7_grctx_oclass;
+void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
+
+extern struct nouveau_oclass *nvd9_grctx_oclass;
+
+extern struct nouveau_oclass *nve4_grctx_oclass;
+extern struct nouveau_oclass *gk20a_grctx_oclass;
+void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
+void nve4_grctx_generate_bundle(struct nvc0_grctx *);
+void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
+void nve4_grctx_generate_unkn(struct nvc0_gr_priv *);
+void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvf0_grctx_oclass;
+extern struct nouveau_oclass *gk110b_grctx_oclass;
+extern struct nouveau_oclass *nv108_grctx_oclass;
+extern struct nouveau_oclass *gm107_grctx_oclass;
+
+/* context init value lists */
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[];
+extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[];
+extern const struct nvc0_gr_init nvc0_grctx_init_main_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[];
+extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[];
+
+extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[];
+extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[];
+extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[];
+extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[];
+
+extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[];
+extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[];
+
+extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[];
+extern const struct nvc0_gr_init nvd9_grctx_init_be_0[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[];
+
+extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[];
+
+extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[];
+extern const struct nvc0_gr_init nve4_grctx_init_ds_0[];
+extern const struct nvc0_gr_init nve4_grctx_init_scc_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_pes_0[];
+
+extern const struct nvc0_gr_pack nve4_grctx_pack_hub[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[];
+extern const struct nvc0_gr_init nve4_grctx_init_a097_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[];
+extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[];
+extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[];
+
+extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[];
+
+extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[];
+
+extern const struct nvc0_gr_init nv108_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[];
+
+
+#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -267,13 +267,13 @@ nvc1_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_icmd[] = {
 	{ nvc1_grctx_init_icmd_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_9097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -575,14 +575,14 @@ nvc1_grctx_init_9097_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_9197_0[] = {
 	{ 0x003400, 128, 0x04, 0x00000000 },
 	{ 0x0002e4,   1, 0x04, 0x0000b001 },
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_mthd[] = {
 	{ nvc1_grctx_init_9097_0, 0x9097 },
 	{ nvc1_grctx_init_9197_0, 0x9197 },
@@ -592,7 +592,7 @@ nvc1_grctx_pack_mthd[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180218 },
@@ -604,7 +604,7 @@ nvc1_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -616,7 +616,7 @@ nvc1_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -628,7 +628,7 @@ nvc1_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvc0_grctx_init_fe_0 },
@@ -642,7 +642,7 @@ nvc1_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x0006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -655,7 +655,7 @@ nvc1_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -665,7 +665,7 @@ nvc1_grctx_init_gpm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvc0_grctx_init_prop_0 },
@@ -678,7 +678,7 @@ nvc1_grctx_pack_gpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_pe_0[] = {
 	{ 0x419818,   1, 0x04, 0x00000000 },
 	{ 0x41983c,   1, 0x04, 0x00038bc7 },
@@ -688,7 +688,7 @@ nvc1_grctx_init_pe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_wwdx_0[] = {
 	{ 0x419b00,   1, 0x04, 0x0a418820 },
 	{ 0x419b04,   1, 0x04, 0x062080e6 },
@@ -702,7 +702,7 @@ nvc1_grctx_init_wwdx_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_tpccs_0[] = {
 	{ 0x419d20,   1, 0x04, 0x12180000 },
 	{ 0x419d24,   1, 0x04, 0x00001fff },
@@ -710,7 +710,7 @@ nvc1_grctx_init_tpccs_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_tpc[] = {
 	{ nvc1_grctx_init_pe_0 },
 	{ nvc4_grctx_init_tex_0 },
@@ -729,7 +729,7 @@ nvc1_grctx_pack_tpc[] = {
 void
 nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
 	const u32  alpha = impl->alpha_nr;
 	const u32   beta = impl->attrib_nr;
@@ -764,7 +764,7 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 void
-nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
 {
 	nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
 	nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -778,12 +778,12 @@ struct nouveau_oclass *
 nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc1_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc4_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -42,7 +42,7 @@ nvc4_grctx_init_tex_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc4_grctx_init_l1c_0[] = {
 	{ 0x419cb0,   1, 0x04, 0x00020048 },
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
@@ -50,7 +50,7 @@ nvc4_grctx_init_l1c_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc4_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000002 },
@@ -64,7 +64,7 @@ nvc4_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc4_grctx_pack_tpc[] = {
 	{ nvc0_grctx_init_pe_0 },
 	{ nvc4_grctx_init_tex_0 },
@@ -84,12 +84,12 @@ struct nouveau_oclass *
 nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc3),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc0_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc8_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -268,19 +268,19 @@ nvc8_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc8_grctx_pack_icmd[] = {
 	{ nvc8_grctx_init_icmd_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc8_grctx_init_9197_0[] = {
 	{ 0x0002e4,   1, 0x04, 0x0000b001 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc8_grctx_init_9297_0[] = {
 	{ 0x003400, 128, 0x04, 0x00000000 },
 	{ 0x00036c,   2, 0x04, 0x00000000 },
@@ -290,7 +290,7 @@ nvc8_grctx_init_9297_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc8_grctx_pack_mthd[] = {
 	{ nvc1_grctx_init_9097_0, 0x9097 },
 	{ nvc8_grctx_init_9197_0, 0x9197 },
@@ -301,7 +301,7 @@ nvc8_grctx_pack_mthd[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc8_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x0006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -314,7 +314,7 @@ nvc8_grctx_init_setup_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc8_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvc0_grctx_init_prop_0 },
@@ -335,12 +335,12 @@ struct nouveau_oclass *
 nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc8),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc0_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180324 },
@@ -41,7 +41,7 @@ nvd7_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -54,7 +54,7 @@ nvd7_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvd9_grctx_init_fe_0 },
@@ -68,7 +68,7 @@ nvd7_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -81,7 +81,7 @@ nvd7_grctx_init_setup_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -94,7 +94,7 @@ nvd7_grctx_pack_gpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd7_grctx_init_pe_0[] = {
 	{ 0x419848,   1, 0x04, 0x00000000 },
 	{ 0x419864,   1, 0x04, 0x00000129 },
@@ -102,7 +102,7 @@ nvd7_grctx_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -116,7 +116,7 @@ nvd7_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000000a },
 	{ 0x419c04,   1, 0x04, 0x00000006 },
@@ -127,7 +127,7 @@ nvd7_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nvd7_grctx_init_tex_0 },
@@ -137,13 +137,13 @@ nvd7_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_pes_0[] = {
 	{ 0x41be24,   1, 0x04, 0x00000002 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x12180000 },
 	{ 0x41bec4,   1, 0x04, 0x00003fff },
@@ -151,7 +151,7 @@ nvd7_grctx_init_cbm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd7_grctx_init_wwdx_0[] = {
 	{ 0x41bf00,   1, 0x04, 0x0a418820 },
 	{ 0x41bf04,   1, 0x04, 0x062080e6 },
@@ -165,7 +165,7 @@ nvd7_grctx_init_wwdx_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_ppc[] = {
 	{ nvd7_grctx_init_pes_0 },
 	{ nvd7_grctx_init_cbm_0 },
@@ -180,7 +180,7 @@ nvd7_grctx_pack_ppc[] = {
 void
 nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
 	const u32  alpha = impl->alpha_nr;
 	const u32   beta = impl->attrib_nr;
@@ -215,18 +215,18 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 void
-nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -244,9 +244,9 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 	for (i = 0; i < 8; i++)
 		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 }
 
@@ -254,12 +254,12 @@ struct nouveau_oclass *
 nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xd7),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvd7_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -270,13 +270,13 @@ nvd9_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvd9_grctx_pack_icmd[] = {
 	{ nvd9_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_90c0_0[] = {
 	{ 0x002700,   8, 0x20, 0x00000000 },
 	{ 0x002704,   8, 0x20, 0x00000000 },
@@ -299,7 +299,7 @@ nvd9_grctx_init_90c0_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvd9_grctx_pack_mthd[] = {
 	{ nvc1_grctx_init_9097_0, 0x9097 },
 	{ nvc8_grctx_init_9197_0, 0x9197 },
@@ -310,7 +310,7 @@ nvd9_grctx_pack_mthd[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_fe_0[] = {
 	{ 0x404004,  10, 0x04, 0x00000000 },
 	{ 0x404044,   1, 0x04, 0x00000000 },
@@ -331,7 +331,7 @@ nvd9_grctx_init_fe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180218 },
@@ -344,7 +344,7 @@ nvd9_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -356,7 +356,7 @@ nvd9_grctx_init_pd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -368,7 +368,7 @@ nvd9_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd9_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvd9_grctx_init_fe_0 },
@@ -382,7 +382,7 @@ nvd9_grctx_pack_hub[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_prop_0[] = {
 	{ 0x418400,   1, 0x04, 0x38004e00 },
 	{ 0x418404,   1, 0x04, 0x71e0ffff },
@@ -395,7 +395,7 @@ nvd9_grctx_init_prop_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000001f },
 	{ 0x418684,   1, 0x04, 0x0000000f },
@@ -405,7 +405,7 @@ nvd9_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -418,7 +418,7 @@ nvd9_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_crstr_0[] = {
 	{ 0x418b00,   1, 0x04, 0x00000006 },
 	{ 0x418b08,   1, 0x04, 0x0a418820 },
@@ -431,7 +431,7 @@ nvd9_grctx_init_crstr_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd9_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -444,7 +444,7 @@ nvd9_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -458,7 +458,7 @@ nvd9_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000000a },
 	{ 0x419c04,   1, 0x04, 0x00000006 },
@@ -469,7 +469,7 @@ nvd9_grctx_init_mpc_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000002 },
@@ -483,7 +483,7 @@ nvd9_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd9_grctx_pack_tpc[] = {
 	{ nvc1_grctx_init_pe_0 },
 	{ nvd9_grctx_init_tex_0 },
@@ -503,12 +503,12 @@ struct nouveau_oclass *
 nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xd9),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc1_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -272,13 +272,13 @@ nve4_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_icmd[] = {
 	{ nve4_grctx_init_icmd_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_a097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -578,14 +578,14 @@ nve4_grctx_init_a097_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nve4_grctx_pack_mthd[] = {
 	{ nve4_grctx_init_a097_0, 0xa097 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_fe_0[] = {
 	{ 0x404010,   5, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -606,7 +606,7 @@ nve4_grctx_init_fe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_memfmt_0[] = {
 	{ 0x404604,   1, 0x04, 0x00000014 },
 	{ 0x404608,   1, 0x04, 0x00000000 },
@@ -632,7 +632,7 @@ nve4_grctx_init_memfmt_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180648 },
@@ -645,14 +645,14 @@ nve4_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_cwd_0[] = {
 	{ 0x405b00,   1, 0x04, 0x00000000 },
 	{ 0x405b10,   1, 0x04, 0x00001000 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x004103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -667,13 +667,13 @@ nve4_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_sked_0[] = {
 	{ 0x407040,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_scc_0[] = {
 	{ 0x408000,   2, 0x04, 0x00000000 },
 	{ 0x408008,   1, 0x04, 0x00000030 },
@@ -684,7 +684,7 @@ nve4_grctx_init_scc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -697,7 +697,7 @@ nve4_grctx_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nve4_grctx_init_fe_0 },
@@ -713,7 +713,7 @@ nve4_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -726,7 +726,7 @@ nve4_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -737,7 +737,7 @@ nve4_grctx_init_gpm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -750,7 +750,7 @@ nve4_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000000f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -765,7 +765,7 @@ nve4_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000000a },
 	{ 0x419c04,   1, 0x04, 0x80000006 },
@@ -776,14 +776,14 @@ nve4_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_l1c_0[] = {
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
 	{ 0x419cf4,   1, 0x04, 0x00003203 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000402 },
@@ -802,7 +802,7 @@ nve4_grctx_init_sm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nve4_grctx_init_tex_0 },
@@ -812,13 +812,13 @@ nve4_grctx_pack_tpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_pes_0[] = {
 	{ 0x41be24,   1, 0x04, 0x00000006 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x12180000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
@@ -826,7 +826,7 @@ nve4_grctx_init_cbm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ nve4_grctx_init_cbm_0 },
@@ -870,7 +870,7 @@ nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
 }
 
 void
-nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv)
 {
 	nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
 	nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -881,7 +881,7 @@ nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
 }
 
 void
-nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
+nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
 {
 	u32 data[6] = {}, data2[2] = {};
 	u8  tpcnr[GPC_MAX];
@@ -939,18 +939,18 @@ nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
 }
 
 void
-nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -977,9 +977,9 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 	}
 	nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
 	nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
@@ -990,12 +990,12 @@ struct nouveau_oclass *
 nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xe4),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -279,13 +279,13 @@ nvf0_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_icmd[] = {
 	{ nvf0_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_a197_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -587,14 +587,14 @@ nvf0_grctx_init_a197_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_mthd[] = {
 	{ nvf0_grctx_init_a197_0, 0xa197 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_fe_0[] = {
 	{ 0x404004,   8, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -620,7 +620,7 @@ nvf0_grctx_init_fe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_pri_0[] = {
 	{ 0x404404,  12, 0x04, 0x00000000 },
 	{ 0x404438,   1, 0x04, 0x00000000 },
@@ -632,7 +632,7 @@ nvf0_grctx_init_pri_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_cwd_0[] = {
 	{ 0x405b00,   1, 0x04, 0x00000000 },
 	{ 0x405b10,   1, 0x04, 0x00001000 },
@@ -640,7 +640,7 @@ nvf0_grctx_init_cwd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x034103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -655,7 +655,7 @@ nvf0_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x12802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -668,7 +668,7 @@ nvf0_grctx_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvf0_grctx_init_fe_0 },
@@ -683,7 +683,7 @@ nvf0_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   1, 0x04, 0x00000000 },
@@ -698,13 +698,13 @@ nvf0_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_gpc_unk_2[] = {
 	{ 0x418d24,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -718,7 +718,7 @@ nvf0_grctx_pack_gpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000000f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -733,7 +733,7 @@ nvf0_grctx_init_tex_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000001a },
 	{ 0x419c04,   1, 0x04, 0x80000006 },
@@ -744,14 +744,14 @@ nvf0_grctx_init_mpc_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_l1c_0[] = {
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
 	{ 0x419cf4,   1, 0x04, 0x00000203 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_sm_0[] = {
 	{ 0x419e04,   1, 0x04, 0x00000000 },
 	{ 0x419e08,   1, 0x04, 0x0000001d },
@@ -779,7 +779,7 @@ nvf0_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvf0_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nvf0_grctx_init_tex_0 },
@@ -789,7 +789,7 @@ nvf0_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x10000000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
@@ -797,7 +797,7 @@ nvf0_grctx_init_cbm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ nvf0_grctx_init_cbm_0 },
@@ -813,12 +813,12 @@ struct nouveau_oclass *
 nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xf0),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c

@@ -29,8 +29,8 @@
  * PGRAPH register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
-gk110b_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+gk110b_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419ca8,   1, 0x04, 0x00000000 },
 	{ 0x419cb0,   1, 0x04, 0x09000000 },
@@ -44,8 +44,8 @@ gk110b_graph_init_l1c_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gk110b_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+gk110b_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000080 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ee4,   1, 0x04, 0x00000000 },
@@ -61,37 +61,37 @@ gk110b_graph_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-gk110b_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvf0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvf0_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ gk110b_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ gk110b_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+gk110b_gr_pack_mmio[] = {
+	{ nve4_gr_init_main_0 },
+	{ nvf0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nvf0_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvf0_gr_init_sked_0 },
+	{ nvf0_gr_init_cwd_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nvf0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nve4_gr_init_tpccs_0 },
+	{ nvf0_gr_init_tex_0 },
+	{ nve4_gr_init_pe_0 },
+	{ gk110b_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ gk110b_gr_init_sm_0 },
+	{ nvd7_gr_init_pes_0 },
+	{ nvd7_gr_init_wwdx_0 },
+	{ nvd7_gr_init_cbm_0 },
+	{ nve4_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -100,18 +100,18 @@ gk110b_graph_pack_mmio[] = {
  ******************************************************************************/
 
 struct nouveau_oclass *
-gk110b_graph_oclass = &(struct nvc0_graph_oclass) {
+gk110b_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xf1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nvf0_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = nvf0_gr_fini,
 	},
 	.cclass = &gk110b_grctx_oclass,
-	.sclass =  nvf0_graph_sclass,
-	.mmio = gk110b_graph_pack_mmio,
-	.fecs.ucode = &nvf0_graph_fecs_ucode,
-	.gpccs.ucode = &nvf0_graph_gpccs_ucode,
+	.sclass =  nvf0_gr_sclass,
+	.mmio = gk110b_gr_pack_mmio,
+	.fecs.ucode = &nvf0_gr_fecs_ucode,
+	.gpccs.ucode = &nvf0_gr_gpccs_ucode,
 	.ppc_nr = 2,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c

@@ -24,25 +24,25 @@
 #include "ctxnvc0.h"
 
 static struct nouveau_oclass
-gk20a_graph_sclass[] = {
+gk20a_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0xa040, &nouveau_object_ofuncs },
-	{ KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ KEPLER_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
 struct nouveau_oclass *
-gk20a_graph_oclass = &(struct nvc0_graph_oclass) {
+gk20a_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xea),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &gk20a_grctx_oclass,
-	.sclass = gk20a_graph_sclass,
-	.mmio = nve4_graph_pack_mmio,
+	.sclass = gk20a_gr_sclass,
+	.mmio = nve4_gr_pack_mmio,
 	.ppc_nr = 1,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c

@@ -33,11 +33,11 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-gm107_graph_sclass[] = {
+gm107_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0xa140, &nouveau_object_ofuncs },
-	{ MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
@@ -45,8 +45,8 @@ gm107_graph_sclass[] = {
  * PGRAPH register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
-gm107_graph_init_main_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_main_0[] = {
 	{ 0x400080,   1, 0x04, 0x003003c2 },
 	{ 0x400088,   1, 0x04, 0x0001bfe7 },
 	{ 0x40008c,   1, 0x04, 0x00060000 },
@@ -61,8 +61,8 @@ gm107_graph_init_main_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_ds_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405900,   1, 0x04, 0x00000000 },
@@ -70,37 +70,37 @@ gm107_graph_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_scc_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_scc_0[] = {
 	{ 0x40803c,   1, 0x04, 0x00000010 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_sked_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_sked_0[] = {
 	{ 0x407010,   1, 0x04, 0x00000000 },
 	{ 0x407040,   1, 0x04, 0x40440424 },
 	{ 0x407048,   1, 0x04, 0x0000000a },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_prop_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_prop_0[] = {
 	{ 0x418408,   1, 0x04, 0x00000000 },
 	{ 0x4184a0,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_setup_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_setup_1[] = {
 	{ 0x4188c8,   2, 0x04, 0x00000000 },
 	{ 0x4188d0,   1, 0x04, 0x00010000 },
 	{ 0x4188d4,   1, 0x04, 0x00010201 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_zcull_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_zcull_0[] = {
 	{ 0x418910,   1, 0x04, 0x00010001 },
 	{ 0x418914,   1, 0x04, 0x00000301 },
 	{ 0x418918,   1, 0x04, 0x00800000 },
@@ -110,8 +110,8 @@ gm107_graph_init_zcull_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_gpc_unk_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_gpc_unk_1[] = {
 	{ 0x418d00,   1, 0x04, 0x00000000 },
 	{ 0x418f00,   1, 0x04, 0x00000400 },
 	{ 0x418f08,   1, 0x04, 0x00000000 },
@@ -119,8 +119,8 @@ gm107_graph_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_tpccs_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_tpccs_0[] = {
 	{ 0x419dc4,   1, 0x04, 0x00000000 },
 	{ 0x419dc8,   1, 0x04, 0x00000501 },
 	{ 0x419dd0,   1, 0x04, 0x00000000 },
@@ -133,8 +133,8 @@ gm107_graph_init_tpccs_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_tex_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_tex_0[] = {
 	{ 0x419ab0,   1, 0x04, 0x00000000 },
 	{ 0x419ab8,   1, 0x04, 0x000000e7 },
 	{ 0x419abc,   1, 0x04, 0x00000000 },
@@ -147,8 +147,8 @@ gm107_graph_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_pe_0[] = {
 	{ 0x419900,   1, 0x04, 0x000000ff },
 	{ 0x41980c,   1, 0x04, 0x00000010 },
 	{ 0x419844,   1, 0x04, 0x00000000 },
@@ -159,15 +159,15 @@ gm107_graph_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419cc0,   2, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_sm_0[] = {
 	{ 0x419e30,   1, 0x04, 0x000000ff },
 	{ 0x419e00,   1, 0x04, 0x00000000 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
@@ -185,16 +185,16 @@ gm107_graph_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_l1c_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_l1c_1[] = {
 	{ 0x419ccc,   2, 0x04, 0x00000000 },
 	{ 0x419c80,   1, 0x04, 0x3f006022 },
 	{ 0x419c88,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_pes_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_pes_0[] = {
 	{ 0x41be50,   1, 0x04, 0x000000ff },
 	{ 0x41be04,   1, 0x04, 0x00000000 },
 	{ 0x41be08,   1, 0x04, 0x00000004 },
@@ -205,21 +205,21 @@ gm107_graph_init_pes_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_wwdx_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_wwdx_0[] = {
 	{ 0x41bfd4,   1, 0x04, 0x00800000 },
 	{ 0x41bfdc,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_cbm_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_cbm_0[] = {
 	{ 0x41becc,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_be_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_be_0[] = {
 	{ 0x408890,   1, 0x04, 0x000000ff },
 	{ 0x40880c,   1, 0x04, 0x00000000 },
 	{ 0x408850,   1, 0x04, 0x00000004 },
@@ -244,45 +244,45 @@ gm107_graph_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gm107_graph_init_sm_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_sm_1[] = {
 	{ 0x419e5c,   1, 0x04, 0x00000000 },
 	{ 0x419e58,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_pack
-gm107_graph_pack_mmio[] = {
-	{ gm107_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ gm107_graph_init_ds_0 },
-	{ gm107_graph_init_scc_0 },
-	{ gm107_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ gm107_graph_init_prop_0 },
-	{ nv108_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ gm107_graph_init_setup_1 },
-	{ gm107_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ gm107_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ gm107_graph_init_tpccs_0 },
-	{ gm107_graph_init_tex_0 },
-	{ gm107_graph_init_pe_0 },
-	{ gm107_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ gm107_graph_init_sm_0 },
-	{ gm107_graph_init_l1c_1 },
-	{ gm107_graph_init_pes_0 },
-	{ gm107_graph_init_wwdx_0 },
-	{ gm107_graph_init_cbm_0 },
-	{ gm107_graph_init_be_0 },
-	{ gm107_graph_init_sm_1 },
+static const struct nvc0_gr_pack
+gm107_gr_pack_mmio[] = {
+	{ gm107_gr_init_main_0 },
+	{ nvf0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvc0_gr_init_pd_0 },
+	{ gm107_gr_init_ds_0 },
+	{ gm107_gr_init_scc_0 },
+	{ gm107_gr_init_sked_0 },
+	{ nvf0_gr_init_cwd_0 },
+	{ gm107_gr_init_prop_0 },
+	{ nv108_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ gm107_gr_init_setup_1 },
+	{ gm107_gr_init_zcull_0 },
+	{ nvc0_gr_init_gpm_0 },
+	{ gm107_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ gm107_gr_init_tpccs_0 },
+	{ gm107_gr_init_tex_0 },
+	{ gm107_gr_init_pe_0 },
+	{ gm107_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ gm107_gr_init_sm_0 },
+	{ gm107_gr_init_l1c_1 },
+	{ gm107_gr_init_pes_0 },
+	{ gm107_gr_init_wwdx_0 },
+	{ gm107_gr_init_cbm_0 },
+	{ gm107_gr_init_be_0 },
+	{ gm107_gr_init_sm_1 },
 	{}
 };
 
@@ -291,7 +291,7 @@ gm107_graph_pack_mmio[] = {
  ******************************************************************************/
 
 static void
-gm107_graph_init_bios(struct nvc0_graph_priv *priv)
+gm107_gr_init_bios(struct nvc0_gr_priv *priv)
 {
 	static const struct {
 		u32 ctrl;
@@ -319,17 +319,17 @@ gm107_graph_init_bios(struct nvc0_graph_priv *priv)
 }
 
 int
-gm107_graph_init(struct nouveau_object *object)
+gm107_gr_init(struct nouveau_object *object)
 {
-	struct nvc0_graph_oclass *oclass = (void *)object->oclass;
-	struct nvc0_graph_priv *priv = (void *)object;
+	struct nvc0_gr_oclass *oclass = (void *)object->oclass;
+	struct nvc0_gr_priv *priv = (void *)object;
 	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
 	u32 data[TPC_MAX / 8] = {};
 	u8  tpcnr[GPC_MAX];
 	int gpc, tpc, ppc, rop;
 	int ret, i;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -339,9 +339,9 @@ gm107_graph_init(struct nouveau_object *object)
 	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
 	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 
-	nvc0_graph_mmio(priv, oclass->mmio);
+	nvc0_gr_mmio(priv, oclass->mmio);
 
-	gm107_graph_init_bios(priv);
+	gm107_gr_init_bios(priv);
 
 	nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
 
@@ -426,15 +426,15 @@ gm107_graph_init(struct nouveau_object *object)
 
 	nv_wr32(priv, 0x400054, 0x2c350f63);
 
-	nvc0_graph_zbc_init(priv);
+	nvc0_gr_zbc_init(priv);
 
-	return nvc0_graph_init_ctxctl(priv);
+	return nvc0_gr_init_ctxctl(priv);
 }
 
 #include "fuc/hubgm107.fuc5.h"
 
-static struct nvc0_graph_ucode
-gm107_graph_fecs_ucode = {
+static struct nvc0_gr_ucode
+gm107_gr_fecs_ucode = {
 	.code.data = gm107_grhub_code,
 	.code.size = sizeof(gm107_grhub_code),
 	.data.data = gm107_grhub_data,
@@ -443,8 +443,8 @@ gm107_graph_fecs_ucode = {
 
 #include "fuc/gpcgm107.fuc5.h"
 
-static struct nvc0_graph_ucode
-gm107_graph_gpccs_ucode = {
+static struct nvc0_gr_ucode
+gm107_gr_gpccs_ucode = {
 	.code.data = gm107_grgpc_code,
 	.code.size = sizeof(gm107_grgpc_code),
 	.data.data = gm107_grgpc_data,
@@ -452,18 +452,18 @@ gm107_graph_gpccs_ucode = {
 };
 
 struct nouveau_oclass *
-gm107_graph_oclass = &(struct nvc0_graph_oclass) {
+gm107_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0x07),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = gm107_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = gm107_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &gm107_grctx_oclass,
-	.sclass =  gm107_graph_sclass,
-	.mmio = gm107_graph_pack_mmio,
-	.fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL,
-	.gpccs.ucode = &gm107_graph_gpccs_ucode,
+	.sclass =  gm107_gr_sclass,
+	.mmio = gm107_gr_pack_mmio,
+	.fecs.ucode = 0 ? &gm107_gr_fecs_ucode : NULL,
+	.gpccs.ucode = &gm107_gr_gpccs_ucode,
 	.ppc_nr = 2,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c

@@ -10,7 +10,7 @@
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
+ * paragr) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
@@ -32,12 +32,12 @@
 #include <subdev/timer.h>
 
 #include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "regs.h"
 
 static u32
-nv04_graph_ctx_regs[] = {
+nv04_gr_ctx_regs[] = {
 	0x0040053c,
 	0x00400544,
 	0x00400540,
@@ -351,21 +351,21 @@ nv04_graph_ctx_regs[] = {
 	NV04_PGRAPH_DEBUG_3
 };
 
-struct nv04_graph_priv {
-	struct nouveau_graph base;
-	struct nv04_graph_chan *chan[16];
+struct nv04_gr_priv {
+	struct nouveau_gr base;
+	struct nv04_gr_chan *chan[16];
 	spinlock_t lock;
 };
 
-struct nv04_graph_chan {
+struct nv04_gr_chan {
 	struct nouveau_object base;
 	int chid;
-	u32 nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
+	u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)];
 };
 
 
-static inline struct nv04_graph_priv *
-nv04_graph_priv(struct nv04_graph_chan *chan)
+static inline struct nv04_gr_priv *
+nv04_gr_priv(struct nv04_gr_chan *chan)
 {
 	return (void *)nv_object(chan)->engine;
 }
@@ -449,9 +449,9 @@ nv04_graph_priv(struct nv04_graph_chan *chan)
  */
 
 static void
-nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
 {
-	struct nv04_graph_priv *priv = (void *)object->engine;
+	struct nv04_gr_priv *priv = (void *)object->engine;
 	int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
 	u32 tmp;
 
@@ -465,7 +465,7 @@ nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
 }
 
 static void
-nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
 {
 	int class, op, valid = 1;
 	u32 tmp, ctx1;
@@ -509,11 +509,11 @@ nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
 		break;
 	}
 
-	nv04_graph_set_ctx1(object, 0x01000000, valid << 24);
+	nv04_gr_set_ctx1(object, 0x01000000, valid << 24);
 }
 
 static int
-nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_set_operation(struct nouveau_object *object, u32 mthd,
 			      void *args, u32 size)
 {
 	u32 class = nv_ro32(object, 0) & 0xff;
@@ -523,17 +523,17 @@ nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd,
 	/* Old versions of the objects only accept first three operations. */
 	if (data > 2 && class < 0x40)
 		return 1;
-	nv04_graph_set_ctx1(object, 0x00038000, data << 15);
+	nv04_gr_set_ctx1(object, 0x00038000, data << 15);
 	/* changing operation changes set of objects needed for validation */
-	nv04_graph_set_ctx_val(object, 0, 0);
+	nv04_gr_set_ctx_val(object, 0, 0);
 	return 0;
 }
 
 static int
-nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
 			      void *args, u32 size)
 {
-	struct nv04_graph_priv *priv = (void *)object->engine;
+	struct nv04_gr_priv *priv = (void *)object->engine;
 	u32 data = *(u32 *)args;
 	u32 min = data & 0xffff, max;
 	u32 w = data >> 16;
@@ -551,10 +551,10 @@ nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
 }
 
 static int
-nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
 			      void *args, u32 size)
 {
-	struct nv04_graph_priv *priv = (void *)object->engine;
+	struct nv04_gr_priv *priv = (void *)object->engine;
 	u32 data = *(u32 *)args;
 	u32 min = data & 0xffff, max;
 	u32 w = data >> 16;
@@ -572,7 +572,7 @@ nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
 }
 
 static u16
-nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
+nv04_gr_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
 {
 	struct nouveau_instmem *imem = nouveau_instmem(object);
 	u32 inst = *(u32 *)args << 4;
@@ -580,380 +580,380 @@ nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
 }
 
 static int
-nv04_graph_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
 			    void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
+		nv04_gr_set_ctx1(object, 0x00004000, 0);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0);
 		return 0;
 	case 0x42:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+		nv04_gr_set_ctx1(object, 0x00004000, 0);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
 				    void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
+		nv04_gr_set_ctx1(object, 0x00004000, 0);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0);
 		return 0;
 	case 0x42:
-		nv04_graph_set_ctx1(object, 0x00004000, 0);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+		nv04_gr_set_ctx1(object, 0x00004000, 0);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
 		return 0;
 	case 0x52:
-		nv04_graph_set_ctx1(object, 0x00004000, 0x00004000);
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+		nv04_gr_set_ctx1(object, 0x00004000, 0x00004000);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv01_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
+nv01_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
 			  void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0);
+		nv04_gr_set_ctx_val(object, 0x08000000, 0);
 		return 0;
 	case 0x18:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000);
+		nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
 			  void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0);
+		nv04_gr_set_ctx_val(object, 0x08000000, 0);
 		return 0;
 	case 0x44:
-		nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000);
+		nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
 			 void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x10000000, 0);
+		nv04_gr_set_ctx_val(object, 0x10000000, 0);
 		return 0;
 	case 0x43:
-		nv04_graph_set_ctx_val(object, 0x10000000, 0x10000000);
+		nv04_gr_set_ctx_val(object, 0x10000000, 0x10000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
 			   void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x20000000, 0);
+		nv04_gr_set_ctx_val(object, 0x20000000, 0);
 		return 0;
 	case 0x12:
-		nv04_graph_set_ctx_val(object, 0x20000000, 0x20000000);
+		nv04_gr_set_ctx_val(object, 0x20000000, 0x20000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
 			   void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x40000000, 0);
+		nv04_gr_set_ctx_val(object, 0x40000000, 0);
 		return 0;
 	case 0x72:
-		nv04_graph_set_ctx_val(object, 0x40000000, 0x40000000);
+		nv04_gr_set_ctx_val(object, 0x40000000, 0x40000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
 			      void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0);
 		return 0;
 	case 0x58:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
 			      void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0);
+		nv04_gr_set_ctx_val(object, 0x04000000, 0);
 		return 0;
 	case 0x59:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000);
+		nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
 				void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0);
 		return 0;
 	case 0x5a:
-		nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+		nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv04_graph_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
 			       void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0);
+		nv04_gr_set_ctx_val(object, 0x04000000, 0);
 		return 0;
 	case 0x5b:
-		nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000);
+		nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv01_graph_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
+nv01_gr_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
 			  void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx1(object, 0x2000, 0);
+		nv04_gr_set_ctx1(object, 0x2000, 0);
 		return 0;
 	case 0x19:
-		nv04_graph_set_ctx1(object, 0x2000, 0x2000);
+		nv04_gr_set_ctx1(object, 0x2000, 0x2000);
 		return 0;
 	}
 	return 1;
 }
 
 static int
-nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
+nv01_gr_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
 			    void *args, u32 size)
 {
-	switch (nv04_graph_mthd_bind_class(object, args, size)) {
+	switch (nv04_gr_mthd_bind_class(object, args, size)) {
 	case 0x30:
-		nv04_graph_set_ctx1(object, 0x1000, 0);
+		nv04_gr_set_ctx1(object, 0x1000, 0);
 		return 0;
 	/* Yes, for some reason even the old versions of objects
 	 * accept 0x57 and not 0x17. Consistency be damned.
 	 */
 	case 0x57:
-		nv04_graph_set_ctx1(object, 0x1000, 0x1000);
+		nv04_gr_set_ctx1(object, 0x1000, 0x1000);
 		return 0;
 	}
 	return 1;
 }
 
 static struct nouveau_omthds
-nv03_graph_gdi_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_patt },
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_rop },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv03_gr_gdi_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_patt },
+	{ 0x0188, 0x0188, nv04_gr_mthd_bind_rop },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_beta1 },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_surf_dst },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_gdi_omthds[] = {
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_gdi_omthds[] = {
+	{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv01_graph_blit_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv01_gr_blit_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+	{ 0x018c, 0x018c, nv01_gr_mthd_bind_patt },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst },
+	{ 0x019c, 0x019c, nv04_gr_mthd_bind_surf_src },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_blit_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_blit_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_patt },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 },
+	{ 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_iifc_omthds[] = {
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_chroma },
-	{ 0x018c, 0x018c, nv01_graph_mthd_bind_clip },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_patt },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_rop },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 },
-	{ 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
-	{ 0x03e4, 0x03e4, nv04_graph_mthd_set_operation },
+nv04_gr_iifc_omthds[] = {
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_chroma },
+	{ 0x018c, 0x018c, nv01_gr_mthd_bind_clip },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_patt },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_rop },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_beta1 },
+	{ 0x019c, 0x019c, nv04_gr_mthd_bind_beta4 },
+	{ 0x01a0, 0x01a0, nv04_gr_mthd_bind_surf2d_swzsurf },
+	{ 0x03e4, 0x03e4, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv01_graph_ifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv01_gr_ifc_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+	{ 0x018c, 0x018c, nv01_gr_mthd_bind_patt },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_ifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
-	{ 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_ifc_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_patt },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 },
+	{ 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv03_graph_sifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv03_gr_sifc_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_sifc_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_sifc_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+	{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv03_graph_sifm_omthds[] = {
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
-	{ 0x0304, 0x0304, nv04_graph_mthd_set_operation },
+nv03_gr_sifm_omthds[] = {
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst },
+	{ 0x0304, 0x0304, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_sifm_omthds[] = {
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x0304, 0x0304, nv04_graph_mthd_set_operation },
+nv04_gr_sifm_omthds[] = {
+	{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+	{ 0x0304, 0x0304, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_surf3d_omthds[] = {
-	{ 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v },
+nv04_gr_surf3d_omthds[] = {
+	{ 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v },
 	{}
 };
 
 static struct nouveau_omthds
-nv03_graph_ttri_omthds[] = {
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta },
+nv03_gr_ttri_omthds[] = {
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_surf_zeta },
 	{}
 };
 
 static struct nouveau_omthds
-nv01_graph_prim_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
-	{ 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv01_gr_prim_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
+	{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static struct nouveau_omthds
-nv04_graph_prim_omthds[] = {
-	{ 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
-	{ 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
-	{ 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
-	{ 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
-	{ 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
-	{ 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
-	{ 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_prim_omthds[] = {
+	{ 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
+	{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+	{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+	{ 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+	{ 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+	{ 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+	{ 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
 	{}
 };
 
 static int
-nv04_graph_object_ctor(struct nouveau_object *parent,
+nv04_gr_object_ctor(struct nouveau_object *parent,
 		       struct nouveau_object *engine,
 		       struct nouveau_oclass *oclass, void *data, u32 size,
 		       struct nouveau_object **pobject)
@@ -978,8 +978,8 @@ nv04_graph_object_ctor(struct nouveau_object *parent,
 }
 
 struct nouveau_ofuncs
-nv04_graph_ofuncs = {
-	.ctor = nv04_graph_object_ctor,
+nv04_gr_ofuncs = {
+	.ctor = nv04_gr_object_ctor,
 	.dtor = _nouveau_gpuobj_dtor,
 	.init = _nouveau_gpuobj_init,
 	.fini = _nouveau_gpuobj_fini,
@@ -988,48 +988,48 @@ nv04_graph_ofuncs = {
 };
 
 static struct nouveau_oclass
-nv04_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0017, &nv04_graph_ofuncs }, /* chroma */
-	{ 0x0018, &nv04_graph_ofuncs }, /* pattern (nv01) */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x001c, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* line */
-	{ 0x001d, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* tri */
-	{ 0x001e, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* rect */
-	{ 0x001f, &nv04_graph_ofuncs, nv01_graph_blit_omthds },
-	{ 0x0021, &nv04_graph_ofuncs, nv01_graph_ifc_omthds },
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0036, &nv04_graph_ofuncs, nv03_graph_sifc_omthds },
-	{ 0x0037, &nv04_graph_ofuncs, nv03_graph_sifm_omthds },
-	{ 0x0038, &nv04_graph_ofuncs }, /* dvd subpicture */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0042, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x0048, &nv04_graph_ofuncs, nv03_graph_ttri_omthds },
-	{ 0x004a, &nv04_graph_ofuncs, nv04_graph_gdi_omthds },
-	{ 0x004b, &nv04_graph_ofuncs, nv03_graph_gdi_omthds },
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x0053, &nv04_graph_ofuncs, nv04_graph_surf3d_omthds },
-	{ 0x0054, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0055, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0057, &nv04_graph_ofuncs }, /* chroma */
-	{ 0x0058, &nv04_graph_ofuncs }, /* surf_dst */
-	{ 0x0059, &nv04_graph_ofuncs }, /* surf_src */
-	{ 0x005a, &nv04_graph_ofuncs }, /* surf_color */
-	{ 0x005b, &nv04_graph_ofuncs }, /* surf_zeta */
-	{ 0x005c, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* line */
-	{ 0x005d, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* tri */
-	{ 0x005e, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* rect */
-	{ 0x005f, &nv04_graph_ofuncs, nv04_graph_blit_omthds },
-	{ 0x0060, &nv04_graph_ofuncs, nv04_graph_iifc_omthds },
-	{ 0x0061, &nv04_graph_ofuncs, nv04_graph_ifc_omthds },
-	{ 0x0064, &nv04_graph_ofuncs }, /* iifc (nv05) */
-	{ 0x0065, &nv04_graph_ofuncs }, /* ifc (nv05) */
-	{ 0x0066, &nv04_graph_ofuncs }, /* sifc (nv05) */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0076, &nv04_graph_ofuncs, nv04_graph_sifc_omthds },
-	{ 0x0077, &nv04_graph_ofuncs, nv04_graph_sifm_omthds },
+nv04_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+	{ 0x0017, &nv04_gr_ofuncs }, /* chroma */
+	{ 0x0018, &nv04_gr_ofuncs }, /* pattern (nv01) */
+	{ 0x0019, &nv04_gr_ofuncs }, /* clip */
+	{ 0x001c, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* line */
+	{ 0x001d, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* tri */
+	{ 0x001e, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* rect */
+	{ 0x001f, &nv04_gr_ofuncs, nv01_gr_blit_omthds },
+	{ 0x0021, &nv04_gr_ofuncs, nv01_gr_ifc_omthds },
+	{ 0x0030, &nv04_gr_ofuncs }, /* null */
+	{ 0x0036, &nv04_gr_ofuncs, nv03_gr_sifc_omthds },
+	{ 0x0037, &nv04_gr_ofuncs, nv03_gr_sifm_omthds },
+	{ 0x0038, &nv04_gr_ofuncs }, /* dvd subpicture */
+	{ 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+	{ 0x0042, &nv04_gr_ofuncs }, /* surf2d */
+	{ 0x0043, &nv04_gr_ofuncs }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs }, /* pattern */
+	{ 0x0048, &nv04_gr_ofuncs, nv03_gr_ttri_omthds },
+	{ 0x004a, &nv04_gr_ofuncs, nv04_gr_gdi_omthds },
+	{ 0x004b, &nv04_gr_ofuncs, nv03_gr_gdi_omthds },
+	{ 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+	{ 0x0053, &nv04_gr_ofuncs, nv04_gr_surf3d_omthds },
+	{ 0x0054, &nv04_gr_ofuncs }, /* ttri */
+	{ 0x0055, &nv04_gr_ofuncs }, /* mtri */
+	{ 0x0057, &nv04_gr_ofuncs }, /* chroma */
+	{ 0x0058, &nv04_gr_ofuncs }, /* surf_dst */
+	{ 0x0059, &nv04_gr_ofuncs }, /* surf_src */
+	{ 0x005a, &nv04_gr_ofuncs }, /* surf_color */
+	{ 0x005b, &nv04_gr_ofuncs }, /* surf_zeta */
+	{ 0x005c, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* line */
+	{ 0x005d, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* tri */
+	{ 0x005e, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* rect */
+	{ 0x005f, &nv04_gr_ofuncs, nv04_gr_blit_omthds },
+	{ 0x0060, &nv04_gr_ofuncs, nv04_gr_iifc_omthds },
+	{ 0x0061, &nv04_gr_ofuncs, nv04_gr_ifc_omthds },
+	{ 0x0064, &nv04_gr_ofuncs }, /* iifc (nv05) */
+	{ 0x0065, &nv04_gr_ofuncs }, /* ifc (nv05) */
+	{ 0x0066, &nv04_gr_ofuncs }, /* sifc (nv05) */
+	{ 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+	{ 0x0076, &nv04_gr_ofuncs, nv04_gr_sifc_omthds },
+	{ 0x0077, &nv04_gr_ofuncs, nv04_gr_sifm_omthds },
 	{},
 };
 
@@ -1037,10 +1037,10 @@ nv04_graph_sclass[] = {
  * PGRAPH context
  ******************************************************************************/
 
-static struct nv04_graph_chan *
-nv04_graph_channel(struct nv04_graph_priv *priv)
+static struct nv04_gr_chan *
+nv04_gr_channel(struct nv04_gr_priv *priv)
 {
-	struct nv04_graph_chan *chan = NULL;
+	struct nv04_gr_chan *chan = NULL;
 	if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
 		int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24;
 		if (chid < ARRAY_SIZE(priv->chan))
@@ -1050,13 +1050,13 @@ nv04_graph_channel(struct nv04_graph_priv *priv)
 }
 
 static int
-nv04_graph_load_context(struct nv04_graph_chan *chan, int chid)
+nv04_gr_load_context(struct nv04_gr_chan *chan, int chid)
 {
-	struct nv04_graph_priv *priv = nv04_graph_priv(chan);
+	struct nv04_gr_priv *priv = nv04_gr_priv(chan);
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
-		nv_wr32(priv, nv04_graph_ctx_regs[i], chan->nv04[i]);
+	for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
+		nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]);
 
 	nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
 	nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
@@ -1065,13 +1065,13 @@ nv04_graph_load_context(struct nv04_graph_chan *chan, int chid)
 }
 
 static int
-nv04_graph_unload_context(struct nv04_graph_chan *chan)
+nv04_gr_unload_context(struct nv04_gr_chan *chan)
 {
-	struct nv04_graph_priv *priv = nv04_graph_priv(chan);
+	struct nv04_gr_priv *priv = nv04_gr_priv(chan);
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
-		chan->nv04[i] = nv_rd32(priv, nv04_graph_ctx_regs[i]);
+	for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
+		chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]);
 
 	nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
 	nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
@@ -1079,36 +1079,36 @@ nv04_graph_unload_context(struct nv04_graph_chan *chan)
 }
 
 static void
-nv04_graph_context_switch(struct nv04_graph_priv *priv)
+nv04_gr_context_switch(struct nv04_gr_priv *priv)
 {
-	struct nv04_graph_chan *prev = NULL;
-	struct nv04_graph_chan *next = NULL;
+	struct nv04_gr_chan *prev = NULL;
+	struct nv04_gr_chan *next = NULL;
 	unsigned long flags;
 	int chid;
 
 	spin_lock_irqsave(&priv->lock, flags);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	/* If previous context is valid, we need to save it */
-	prev = nv04_graph_channel(priv);
+	prev = nv04_gr_channel(priv);
 	if (prev)
-		nv04_graph_unload_context(prev);
+		nv04_gr_unload_context(prev);
 
 	/* load context for next channel */
 	chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
 	next = priv->chan[chid];
 	if (next)
-		nv04_graph_load_context(next, chid);
+		nv04_gr_load_context(next, chid);
 
 	spin_unlock_irqrestore(&priv->lock, flags);
 }
 
-static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg)
+static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg)
 {
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
-		if (nv04_graph_ctx_regs[i] == reg)
+	for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) {
+		if (nv04_gr_ctx_regs[i] == reg)
 			return &chan->nv04[i];
 	}
 
@@ -1116,14 +1116,14 @@ static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg)
 }
 
 static int
-nv04_graph_context_ctor(struct nouveau_object *parent,
+nv04_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
 	struct nouveau_fifo_chan *fifo = (void *)parent;
-	struct nv04_graph_priv *priv = (void *)engine;
-	struct nv04_graph_chan *chan;
+	struct nv04_gr_priv *priv = (void *)engine;
+	struct nv04_gr_chan *chan;
 	unsigned long flags;
 	int ret;
 
@@ -1150,10 +1150,10 @@ nv04_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static void
-nv04_graph_context_dtor(struct nouveau_object *object)
+nv04_gr_context_dtor(struct nouveau_object *object)
 {
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	struct nv04_graph_chan *chan = (void *)object;
+	struct nv04_gr_priv *priv = (void *)object->engine;
+	struct nv04_gr_chan *chan = (void *)object;
 	unsigned long flags;
 
 	spin_lock_irqsave(&priv->lock, flags);
@@ -1164,16 +1164,16 @@ nv04_graph_context_dtor(struct nouveau_object *object)
 }
 
 static int
-nv04_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv04_gr_context_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nv04_graph_priv *priv = (void *)object->engine;
-	struct nv04_graph_chan *chan = (void *)object;
+	struct nv04_gr_priv *priv = (void *)object->engine;
+	struct nv04_gr_chan *chan = (void *)object;
 	unsigned long flags;
 
 	spin_lock_irqsave(&priv->lock, flags);
 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
-	if (nv04_graph_channel(priv) == chan)
-		nv04_graph_unload_context(chan);
+	if (nv04_gr_channel(priv) == chan)
+		nv04_gr_unload_context(chan);
 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
 	spin_unlock_irqrestore(&priv->lock, flags);
 
@@ -1181,13 +1181,13 @@ nv04_graph_context_fini(struct nouveau_object *object, bool suspend)
 }
 
 static struct nouveau_oclass
-nv04_graph_cclass = {
+nv04_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x04),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_graph_context_ctor,
-		.dtor = nv04_graph_context_dtor,
+		.ctor = nv04_gr_context_ctor,
+		.dtor = nv04_gr_context_dtor,
 		.init = nouveau_object_init,
-		.fini = nv04_graph_context_fini,
+		.fini = nv04_gr_context_fini,
 	},
 };
 
@@ -1196,17 +1196,17 @@ nv04_graph_cclass = {
  ******************************************************************************/
 
 bool
-nv04_graph_idle(void *obj)
+nv04_gr_idle(void *obj)
 {
-	struct nouveau_graph *graph = nouveau_graph(obj);
+	struct nouveau_gr *gr = nouveau_gr(obj);
 	u32 mask = 0xffffffff;
 
 	if (nv_device(obj)->card_type == NV_40)
 		mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
 
-	if (!nv_wait(graph, NV04_PGRAPH_STATUS, mask, 0)) {
-		nv_error(graph, "idle timed out with status 0x%08x\n",
-			 nv_rd32(graph, NV04_PGRAPH_STATUS));
+	if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) {
+		nv_error(gr, "idle timed out with status 0x%08x\n",
+			 nv_rd32(gr, NV04_PGRAPH_STATUS));
 		return false;
 	}
 
@@ -1214,13 +1214,13 @@ nv04_graph_idle(void *obj)
 }
 
 static const struct nouveau_bitfield
-nv04_graph_intr_name[] = {
+nv04_gr_intr_name[] = {
 	{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
 	{}
 };
 
 static const struct nouveau_bitfield
-nv04_graph_nstatus[] = {
+nv04_gr_nstatus[] = {
 	{ NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 	{ NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 	{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
@@ -1229,7 +1229,7 @@ nv04_graph_nstatus[] = {
 };
 
 const struct nouveau_bitfield
-nv04_graph_nsource[] = {
+nv04_gr_nsource[] = {
 	{ NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
 	{ NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
 	{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
@@ -1253,10 +1253,10 @@ nv04_graph_nsource[] = {
 };
 
 static void
-nv04_graph_intr(struct nouveau_subdev *subdev)
+nv04_gr_intr(struct nouveau_subdev *subdev)
 {
-	struct nv04_graph_priv *priv = (void *)subdev;
-	struct nv04_graph_chan *chan = NULL;
+	struct nv04_gr_priv *priv = (void *)subdev;
+	struct nv04_gr_chan *chan = NULL;
 	struct nouveau_namedb *namedb = NULL;
 	struct nouveau_handle *handle = NULL;
 	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
@@ -1290,7 +1290,7 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
 		nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
 		stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
 		show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-		nv04_graph_context_switch(priv);
+		nv04_gr_context_switch(priv);
 	}
 
 	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
@@ -1298,11 +1298,11 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
 
 	if (show) {
 		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv04_graph_intr_name, show);
+		nouveau_bitfield_print(nv04_gr_intr_name, show);
 		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
+		nouveau_bitfield_print(nv04_gr_nsource, nsource);
 		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
+		nouveau_bitfield_print(nv04_gr_nstatus, nstatus);
 		pr_cont("\n");
 		nv_error(priv,
 			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -1314,34 +1314,34 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv04_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
-	struct nv04_graph_priv *priv;
+	struct nv04_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv04_graph_intr;
-	nv_engine(priv)->cclass = &nv04_graph_cclass;
-	nv_engine(priv)->sclass = nv04_graph_sclass;
+	nv_subdev(priv)->intr = nv04_gr_intr;
+	nv_engine(priv)->cclass = &nv04_gr_cclass;
+	nv_engine(priv)->sclass = nv04_gr_sclass;
 	spin_lock_init(&priv->lock);
 	return 0;
 }
 
 static int
-nv04_graph_init(struct nouveau_object *object)
+nv04_gr_init(struct nouveau_object *object)
 {
 	struct nouveau_engine *engine = nv_engine(object);
-	struct nv04_graph_priv *priv = (void *)engine;
+	struct nv04_gr_priv *priv = (void *)engine;
 	int ret;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -1377,12 +1377,12 @@ nv04_graph_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv04_graph_oclass = {
+nv04_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x04),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv04_graph_ctor,
-		.dtor = _nouveau_graph_dtor,
-		.init = nv04_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv04_gr_ctor,
+		.dtor = _nouveau_gr_dtor,
+		.init = nv04_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

@@ -10,7 +10,7 @@
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
+ * paragr) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
@@ -29,7 +29,7 @@
 #include <subdev/fb.h>
 
 #include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "regs.h"
 
@@ -46,7 +46,7 @@ struct pipe_state {
 	u32 pipe_0x7800[0x0c0/4];
 };
 
-static int nv10_graph_ctx_regs[] = {
+static int nv10_gr_ctx_regs[] = {
 	NV10_PGRAPH_CTX_SWITCH(0),
 	NV10_PGRAPH_CTX_SWITCH(1),
 	NV10_PGRAPH_CTX_SWITCH(2),
@@ -368,7 +368,7 @@ static int nv10_graph_ctx_regs[] = {
 	NV04_PGRAPH_VALID2,
 };
 
-static int nv17_graph_ctx_regs[] = {
+static int nv17_gr_ctx_regs[] = {
 	NV10_PGRAPH_DEBUG_4,
 	0x004006b0,
 	0x00400eac,
@@ -389,24 +389,24 @@ static int nv17_graph_ctx_regs[] = {
 	0x00400a04,
 };
 
-struct nv10_graph_priv {
-	struct nouveau_graph base;
-	struct nv10_graph_chan *chan[32];
+struct nv10_gr_priv {
+	struct nouveau_gr base;
+	struct nv10_gr_chan *chan[32];
 	spinlock_t lock;
 };
 
-struct nv10_graph_chan {
+struct nv10_gr_chan {
 	struct nouveau_object base;
 	int chid;
-	int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
-	int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
+	int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)];
+	int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)];
 	struct pipe_state pipe_state;
 	u32 lma_window[4];
 };
 
 
-static inline struct nv10_graph_priv *
-nv10_graph_priv(struct nv10_graph_chan *chan)
+static inline struct nv10_gr_priv *
+nv10_gr_priv(struct nv10_gr_chan *chan)
 {
 	return (void *)nv_object(chan)->engine;
 }
@@ -432,57 +432,57 @@ nv10_graph_priv(struct nv10_graph_chan *chan)
 	} while (0)
 
 static struct nouveau_oclass
-nv10_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x004a, &nv04_graph_ofuncs }, /* gdi */
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x005f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0062, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0093, &nv04_graph_ofuncs }, /* surf3d */
-	{ 0x0094, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0095, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0056, &nv04_graph_ofuncs }, /* celcius */
+nv10_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs }, /* pattern */
+	{ 0x004a, &nv04_gr_ofuncs }, /* gdi */
+	{ 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+	{ 0x005f, &nv04_gr_ofuncs }, /* blit */
+	{ 0x0062, &nv04_gr_ofuncs }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs }, /* ifc */
+	{ 0x009f, &nv04_gr_ofuncs }, /* blit */
+	{ 0x0093, &nv04_gr_ofuncs }, /* surf3d */
+	{ 0x0094, &nv04_gr_ofuncs }, /* ttri */
+	{ 0x0095, &nv04_gr_ofuncs }, /* mtri */
+	{ 0x0056, &nv04_gr_ofuncs }, /* celcius */
 	{},
 };
 
 static struct nouveau_oclass
-nv15_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x004a, &nv04_graph_ofuncs }, /* gdi */
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x005f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0062, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0093, &nv04_graph_ofuncs }, /* surf3d */
-	{ 0x0094, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0095, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0096, &nv04_graph_ofuncs }, /* celcius */
+nv15_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs }, /* pattern */
+	{ 0x004a, &nv04_gr_ofuncs }, /* gdi */
+	{ 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+	{ 0x005f, &nv04_gr_ofuncs }, /* blit */
+	{ 0x0062, &nv04_gr_ofuncs }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs }, /* ifc */
+	{ 0x009f, &nv04_gr_ofuncs }, /* blit */
+	{ 0x0093, &nv04_gr_ofuncs }, /* surf3d */
+	{ 0x0094, &nv04_gr_ofuncs }, /* ttri */
+	{ 0x0095, &nv04_gr_ofuncs }, /* mtri */
+	{ 0x0096, &nv04_gr_ofuncs }, /* celcius */
 	{},
 };
 
 static int
-nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
+nv17_gr_mthd_lma_window(struct nouveau_object *object, u32 mthd,
 			   void *args, u32 size)
 {
-	struct nv10_graph_chan *chan = (void *)object->parent;
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_chan *chan = (void *)object->parent;
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	struct pipe_state *pipe = &chan->pipe_state;
 	u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
 	u32 xfmode0, xfmode1;
@@ -494,14 +494,14 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
 	if (mthd != 0x1644)
 		return 0;
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	PIPE_SAVE(priv, pipe_0x0040, 0x0040);
 	PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);
 
 	PIPE_RESTORE(priv, chan->lma_window, 0x6790);
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
 	xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
@@ -511,7 +511,7 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
 	PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0);
 	PIPE_SAVE(priv, pipe_0x6a80, 0x6a80);
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);
 	nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);
@@ -534,7 +534,7 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
 
 	PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	PIPE_RESTORE(priv, pipe_0x0040, 0x0040);
 
@@ -549,19 +549,19 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
 	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	return 0;
 }
 
 static int
-nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
+nv17_gr_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
 			   void *args, u32 size)
 {
-	struct nv10_graph_chan *chan = (void *)object->parent;
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_chan *chan = (void *)object->parent;
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
 	nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000);
@@ -570,34 +570,34 @@ nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
 
 static struct nouveau_omthds
 nv17_celcius_omthds[] = {
-	{ 0x1638, 0x1638, nv17_graph_mthd_lma_window },
-	{ 0x163c, 0x163c, nv17_graph_mthd_lma_window },
-	{ 0x1640, 0x1640, nv17_graph_mthd_lma_window },
-	{ 0x1644, 0x1644, nv17_graph_mthd_lma_window },
-	{ 0x1658, 0x1658, nv17_graph_mthd_lma_enable },
+	{ 0x1638, 0x1638, nv17_gr_mthd_lma_window },
+	{ 0x163c, 0x163c, nv17_gr_mthd_lma_window },
+	{ 0x1640, 0x1640, nv17_gr_mthd_lma_window },
+	{ 0x1644, 0x1644, nv17_gr_mthd_lma_window },
+	{ 0x1658, 0x1658, nv17_gr_mthd_lma_enable },
 	{}
 };
 
 static struct nouveau_oclass
-nv17_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs }, /* pattern */
-	{ 0x004a, &nv04_graph_ofuncs }, /* gdi */
-	{ 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
-	{ 0x005f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0062, &nv04_graph_ofuncs }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs }, /* blit */
-	{ 0x0093, &nv04_graph_ofuncs }, /* surf3d */
-	{ 0x0094, &nv04_graph_ofuncs }, /* ttri */
-	{ 0x0095, &nv04_graph_ofuncs }, /* mtri */
-	{ 0x0099, &nv04_graph_ofuncs, nv17_celcius_omthds },
+nv17_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs }, /* pattern */
+	{ 0x004a, &nv04_gr_ofuncs }, /* gdi */
+	{ 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+	{ 0x005f, &nv04_gr_ofuncs }, /* blit */
+	{ 0x0062, &nv04_gr_ofuncs }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs }, /* ifc */
+	{ 0x009f, &nv04_gr_ofuncs }, /* blit */
+	{ 0x0093, &nv04_gr_ofuncs }, /* surf3d */
+	{ 0x0094, &nv04_gr_ofuncs }, /* ttri */
+	{ 0x0095, &nv04_gr_ofuncs }, /* mtri */
+	{ 0x0099, &nv04_gr_ofuncs, nv17_celcius_omthds },
 	{},
 };
 
@@ -605,10 +605,10 @@ nv17_graph_sclass[] = {
  * PGRAPH context
  ******************************************************************************/
 
-static struct nv10_graph_chan *
-nv10_graph_channel(struct nv10_graph_priv *priv)
+static struct nv10_gr_chan *
+nv10_gr_channel(struct nv10_gr_priv *priv)
 {
-	struct nv10_graph_chan *chan = NULL;
+	struct nv10_gr_chan *chan = NULL;
 	if (nv_rd32(priv, 0x400144) & 0x00010000) {
 		int chid = nv_rd32(priv, 0x400148) >> 24;
 		if (chid < ARRAY_SIZE(priv->chan))
@@ -618,9 +618,9 @@ nv10_graph_channel(struct nv10_graph_priv *priv)
 }
 
 static void
-nv10_graph_save_pipe(struct nv10_graph_chan *chan)
+nv10_gr_save_pipe(struct nv10_gr_chan *chan)
 {
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	struct pipe_state *pipe = &chan->pipe_state;
 
 	PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);
@@ -636,14 +636,14 @@ nv10_graph_save_pipe(struct nv10_graph_chan *chan)
 }
 
 static void
-nv10_graph_load_pipe(struct nv10_graph_chan *chan)
+nv10_gr_load_pipe(struct nv10_gr_chan *chan)
 {
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	struct pipe_state *pipe = &chan->pipe_state;
 	u32 xfmode0, xfmode1;
 	int i;
 
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 	/* XXX check haiku comments */
 	xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
 	xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
@@ -668,7 +668,7 @@ nv10_graph_load_pipe(struct nv10_graph_chan *chan)
 
 
 	PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	/* restore XFMODE */
 	nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);
@@ -682,13 +682,13 @@ nv10_graph_load_pipe(struct nv10_graph_chan *chan)
 	PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);
 	PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000);
 	PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 }
 
 static void
-nv10_graph_create_pipe(struct nv10_graph_chan *chan)
+nv10_gr_create_pipe(struct nv10_gr_chan *chan)
 {
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	struct pipe_state *pipe_state = &chan->pipe_state;
 	u32 *pipe_state_addr;
 	int i;
@@ -841,11 +841,11 @@ nv10_graph_create_pipe(struct nv10_graph_chan *chan)
 }
 
 static int
-nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
+nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)
 {
 	int i;
-	for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) {
-		if (nv10_graph_ctx_regs[i] == reg)
+	for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
+		if (nv10_gr_ctx_regs[i] == reg)
 			return i;
 	}
 	nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg);
@@ -853,11 +853,11 @@ nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
 }
 
 static int
-nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
+nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)
 {
 	int i;
-	for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) {
-		if (nv17_graph_ctx_regs[i] == reg)
+	for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
+		if (nv17_gr_ctx_regs[i] == reg)
 			return i;
 	}
 	nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg);
@@ -865,9 +865,9 @@ nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
 }
 
 static void
-nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst)
+nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst)
 {
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
 	u32 ctx_user, ctx_switch[5];
 	int i, subchan = -1;
@@ -935,25 +935,25 @@ nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst)
 }
 
 static int
-nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
+nv10_gr_load_context(struct nv10_gr_chan *chan, int chid)
 {
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	u32 inst;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
-		nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]);
+	for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
+		nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]);
 
 	if (nv_device(priv)->card_type >= NV_11 &&
 	    nv_device(priv)->chipset >= 0x17) {
-		for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
-			nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]);
+		for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
+			nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]);
 	}
 
-	nv10_graph_load_pipe(chan);
+	nv10_gr_load_pipe(chan);
 
 	inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
-	nv10_graph_load_dma_vtxbuf(chan, chid, inst);
+	nv10_gr_load_dma_vtxbuf(chan, chid, inst);
 
 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
@@ -962,21 +962,21 @@ nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
 }
 
 static int
-nv10_graph_unload_context(struct nv10_graph_chan *chan)
+nv10_gr_unload_context(struct nv10_gr_chan *chan)
 {
-	struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+	struct nv10_gr_priv *priv = nv10_gr_priv(chan);
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
-		chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]);
+	for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
+		chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]);
 
 	if (nv_device(priv)->card_type >= NV_11 &&
 	    nv_device(priv)->chipset >= 0x17) {
-		for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
-			chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]);
+		for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
+			chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]);
 	}
 
-	nv10_graph_save_pipe(chan);
+	nv10_gr_save_pipe(chan);
 
 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
 	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
@@ -984,51 +984,51 @@ nv10_graph_unload_context(struct nv10_graph_chan *chan)
 }
 
 static void
-nv10_graph_context_switch(struct nv10_graph_priv *priv)
+nv10_gr_context_switch(struct nv10_gr_priv *priv)
 {
-	struct nv10_graph_chan *prev = NULL;
-	struct nv10_graph_chan *next = NULL;
+	struct nv10_gr_chan *prev = NULL;
+	struct nv10_gr_chan *next = NULL;
 	unsigned long flags;
 	int chid;
 
 	spin_lock_irqsave(&priv->lock, flags);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	/* If previous context is valid, we need to save it */
-	prev = nv10_graph_channel(priv);
+	prev = nv10_gr_channel(priv);
 	if (prev)
-		nv10_graph_unload_context(prev);
+		nv10_gr_unload_context(prev);
 
 	/* load context for next channel */
 	chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
 	next = priv->chan[chid];
 	if (next)
-		nv10_graph_load_context(next, chid);
+		nv10_gr_load_context(next, chid);
 
 	spin_unlock_irqrestore(&priv->lock, flags);
 }
 
 #define NV_WRITE_CTX(reg, val) do { \
-	int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \
+	int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \
 	if (offset > 0) \
 		chan->nv10[offset] = val; \
 	} while (0)
 
 #define NV17_WRITE_CTX(reg, val) do { \
-	int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \
+	int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \
 	if (offset > 0) \
 		chan->nv17[offset] = val; \
 	} while (0)
 
 static int
-nv10_graph_context_ctor(struct nouveau_object *parent,
+nv10_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
 	struct nouveau_fifo_chan *fifo = (void *)parent;
-	struct nv10_graph_priv *priv = (void *)engine;
-	struct nv10_graph_chan *chan;
+	struct nv10_gr_priv *priv = (void *)engine;
+	struct nv10_gr_chan *chan;
 	unsigned long flags;
 	int ret;
 
@@ -1066,7 +1066,7 @@ nv10_graph_context_ctor(struct nouveau_object *parent,
 	}
 	NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24);
 
-	nv10_graph_create_pipe(chan);
+	nv10_gr_create_pipe(chan);
 
 	priv->chan[fifo->chid] = chan;
 	chan->chid = fifo->chid;
@@ -1075,10 +1075,10 @@ nv10_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static void
-nv10_graph_context_dtor(struct nouveau_object *object)
+nv10_gr_context_dtor(struct nouveau_object *object)
 {
-	struct nv10_graph_priv *priv = (void *)object->engine;
-	struct nv10_graph_chan *chan = (void *)object;
+	struct nv10_gr_priv *priv = (void *)object->engine;
+	struct nv10_gr_chan *chan = (void *)object;
 	unsigned long flags;
 
 	spin_lock_irqsave(&priv->lock, flags);
@@ -1089,16 +1089,16 @@ nv10_graph_context_dtor(struct nouveau_object *object)
 }
 
 static int
-nv10_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_context_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nv10_graph_priv *priv = (void *)object->engine;
-	struct nv10_graph_chan *chan = (void *)object;
+	struct nv10_gr_priv *priv = (void *)object->engine;
+	struct nv10_gr_chan *chan = (void *)object;
 	unsigned long flags;
 
 	spin_lock_irqsave(&priv->lock, flags);
 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
-	if (nv10_graph_channel(priv) == chan)
-		nv10_graph_unload_context(chan);
+	if (nv10_gr_channel(priv) == chan)
+		nv10_gr_unload_context(chan);
 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
 	spin_unlock_irqrestore(&priv->lock, flags);
 
@@ -1106,13 +1106,13 @@ nv10_graph_context_fini(struct nouveau_object *object, bool suspend)
 }
 
 static struct nouveau_oclass
-nv10_graph_cclass = {
+nv10_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x10),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_graph_context_ctor,
-		.dtor = nv10_graph_context_dtor,
+		.ctor = nv10_gr_context_ctor,
+		.dtor = nv10_gr_context_dtor,
 		.init = nouveau_object_init,
-		.fini = nv10_graph_context_fini,
+		.fini = nv10_gr_context_fini,
 	},
 };
 
@@ -1121,15 +1121,15 @@ nv10_graph_cclass = {
  ******************************************************************************/
 
 static void
-nv10_graph_tile_prog(struct nouveau_engine *engine, int i)
+nv10_gr_tile_prog(struct nouveau_engine *engine, int i)
 {
 	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
 	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
-	struct nv10_graph_priv *priv = (void *)engine;
+	struct nv10_gr_priv *priv = (void *)engine;
 	unsigned long flags;
 
 	pfifo->pause(pfifo, &flags);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit);
 	nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch);
@@ -1138,13 +1138,13 @@ nv10_graph_tile_prog(struct nouveau_engine *engine, int i)
 	pfifo->start(pfifo, &flags);
 }
 
-const struct nouveau_bitfield nv10_graph_intr_name[] = {
+const struct nouveau_bitfield nv10_gr_intr_name[] = {
 	{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
 	{ NV_PGRAPH_INTR_ERROR,  "ERROR"  },
 	{}
 };
 
-const struct nouveau_bitfield nv10_graph_nstatus[] = {
+const struct nouveau_bitfield nv10_gr_nstatus[] = {
 	{ NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 	{ NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 	{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
@@ -1153,10 +1153,10 @@ const struct nouveau_bitfield nv10_graph_nstatus[] = {
 };
 
 static void
-nv10_graph_intr(struct nouveau_subdev *subdev)
+nv10_gr_intr(struct nouveau_subdev *subdev)
 {
-	struct nv10_graph_priv *priv = (void *)subdev;
-	struct nv10_graph_chan *chan = NULL;
+	struct nv10_gr_priv *priv = (void *)subdev;
+	struct nv10_gr_chan *chan = NULL;
 	struct nouveau_namedb *namedb = NULL;
 	struct nouveau_handle *handle = NULL;
 	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
@@ -1189,7 +1189,7 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
 		nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
 		stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
 		show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-		nv10_graph_context_switch(priv);
+		nv10_gr_context_switch(priv);
 	}
 
 	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
@@ -1197,11 +1197,11 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
 
 	if (show) {
 		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv10_graph_intr_name, show);
+		nouveau_bitfield_print(nv10_gr_intr_name, show);
 		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
+		nouveau_bitfield_print(nv04_gr_nsource, nsource);
 		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+		nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
 		pr_cont("\n");
 		nv_error(priv,
 			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -1213,52 +1213,52 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv10_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *oclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
-	struct nv10_graph_priv *priv;
+	struct nv10_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv10_graph_intr;
-	nv_engine(priv)->cclass = &nv10_graph_cclass;
+	nv_subdev(priv)->intr = nv10_gr_intr;
+	nv_engine(priv)->cclass = &nv10_gr_cclass;
 
 	if (nv_device(priv)->chipset <= 0x10)
-		nv_engine(priv)->sclass = nv10_graph_sclass;
+		nv_engine(priv)->sclass = nv10_gr_sclass;
 	else
 	if (nv_device(priv)->chipset <  0x17 ||
 	    nv_device(priv)->card_type < NV_11)
-		nv_engine(priv)->sclass = nv15_graph_sclass;
+		nv_engine(priv)->sclass = nv15_gr_sclass;
 	else
-		nv_engine(priv)->sclass = nv17_graph_sclass;
+		nv_engine(priv)->sclass = nv17_gr_sclass;
 
-	nv_engine(priv)->tile_prog = nv10_graph_tile_prog;
+	nv_engine(priv)->tile_prog = nv10_gr_tile_prog;
 	spin_lock_init(&priv->lock);
 	return 0;
 }
 
 static void
-nv10_graph_dtor(struct nouveau_object *object)
+nv10_gr_dtor(struct nouveau_object *object)
 {
-	struct nv10_graph_priv *priv = (void *)object;
-	nouveau_graph_destroy(&priv->base);
+	struct nv10_gr_priv *priv = (void *)object;
+	nouveau_gr_destroy(&priv->base);
 }
 
 static int
-nv10_graph_init(struct nouveau_object *object)
+nv10_gr_init(struct nouveau_object *object)
 {
 	struct nouveau_engine *engine = nv_engine(object);
 	struct nouveau_fb *pfb = nouveau_fb(object);
-	struct nv10_graph_priv *priv = (void *)engine;
+	struct nv10_gr_priv *priv = (void *)engine;
 	int ret, i;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -1301,19 +1301,19 @@ nv10_graph_init(struct nouveau_object *object)
 }
 
 static int
-nv10_graph_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nv10_graph_priv *priv = (void *)object;
-	return nouveau_graph_fini(&priv->base, suspend);
+	struct nv10_gr_priv *priv = (void *)object;
+	return nouveau_gr_fini(&priv->base, suspend);
 }
 
 struct nouveau_oclass
-nv10_graph_oclass = {
+nv10_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x10),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv10_graph_ctor,
-		.dtor = nv10_graph_dtor,
-		.init = nv10_graph_init,
-		.fini = nv10_graph_fini,
+		.ctor = nv10_gr_ctor,
+		.dtor = nv10_gr_dtor,
+		.init = nv10_gr_init,
+		.fini = nv10_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c

@@ -30,7 +30,7 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nv108_graph_sclass[] = {
+nv108_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0xa140, &nouveau_object_ofuncs },
 	{ KEPLER_B, &nvc0_fermi_ofuncs },
@@ -42,8 +42,8 @@ nv108_graph_sclass[] = {
  * PGRAPH register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
-nv108_graph_init_main_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_main_0[] = {
 	{ 0x400080,   1, 0x04, 0x003083c2 },
 	{ 0x400088,   1, 0x04, 0x0001bfe7 },
 	{ 0x40008c,   1, 0x04, 0x00000000 },
@@ -58,8 +58,8 @@ nv108_graph_init_main_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nv108_graph_init_ds_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405900,   1, 0x04, 0x00000000 },
@@ -68,8 +68,8 @@ nv108_graph_init_ds_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nv108_graph_init_gpc_unk_0[] = {
+const struct nvc0_gr_init
+nv108_gr_init_gpc_unk_0[] = {
 	{ 0x418604,   1, 0x04, 0x00000000 },
 	{ 0x418680,   1, 0x04, 0x00000000 },
 	{ 0x418714,   1, 0x04, 0x00000000 },
@@ -77,16 +77,16 @@ nv108_graph_init_gpc_unk_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nv108_graph_init_setup_1[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_setup_1[] = {
 	{ 0x4188c8,   2, 0x04, 0x00000000 },
 	{ 0x4188d0,   1, 0x04, 0x00010000 },
 	{ 0x4188d4,   1, 0x04, 0x00000201 },
 	{}
 };
 
-static const struct nvc0_graph_init
-nv108_graph_init_tex_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_tex_0[] = {
 	{ 0x419ab0,   1, 0x04, 0x00000000 },
 	{ 0x419ac8,   1, 0x04, 0x00000000 },
 	{ 0x419ab8,   1, 0x04, 0x000000e7 },
@@ -96,8 +96,8 @@ nv108_graph_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nv108_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419ca8,   1, 0x04, 0x00000000 },
 	{ 0x419cb0,   1, 0x04, 0x01000000 },
@@ -111,37 +111,37 @@ nv108_graph_init_l1c_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-nv108_graph_pack_mmio[] = {
-	{ nv108_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nv108_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nv108_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nv108_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nv108_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ nv108_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvf0_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nv108_gr_pack_mmio[] = {
+	{ nv108_gr_init_main_0 },
+	{ nvf0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nv108_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvf0_gr_init_sked_0 },
+	{ nvf0_gr_init_cwd_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nv108_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nv108_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nvf0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nve4_gr_init_tpccs_0 },
+	{ nv108_gr_init_tex_0 },
+	{ nve4_gr_init_pe_0 },
+	{ nv108_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvf0_gr_init_sm_0 },
+	{ nvd7_gr_init_pes_0 },
+	{ nvd7_gr_init_wwdx_0 },
+	{ nvd7_gr_init_cbm_0 },
+	{ nve4_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -150,9 +150,9 @@ nv108_graph_pack_mmio[] = {
  ******************************************************************************/
 
 static int
-nv108_graph_fini(struct nouveau_object *object, bool suspend)
+nv108_gr_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nvc0_graph_priv *priv = (void *)object;
+	struct nvc0_gr_priv *priv = (void *)object;
 	static const struct {
 		u32 addr;
 		u32 data;
@@ -183,13 +183,13 @@ nv108_graph_fini(struct nouveau_object *object, bool suspend)
 		nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
 	}
 
-	return nouveau_graph_fini(&priv->base, suspend);
+	return nouveau_gr_fini(&priv->base, suspend);
 }
 
 #include "fuc/hubnv108.fuc5.h"
 
-static struct nvc0_graph_ucode
-nv108_graph_fecs_ucode = {
+static struct nvc0_gr_ucode
+nv108_gr_fecs_ucode = {
 	.code.data = nv108_grhub_code,
 	.code.size = sizeof(nv108_grhub_code),
 	.data.data = nv108_grhub_data,
@@ -198,8 +198,8 @@ nv108_graph_fecs_ucode = {
 
 #include "fuc/gpcnv108.fuc5.h"
 
-static struct nvc0_graph_ucode
-nv108_graph_gpccs_ucode = {
+static struct nvc0_gr_ucode
+nv108_gr_gpccs_ucode = {
 	.code.data = nv108_grgpc_code,
 	.code.size = sizeof(nv108_grgpc_code),
 	.data.data = nv108_grgpc_data,
@@ -207,18 +207,18 @@ nv108_graph_gpccs_ucode = {
 };
 
 struct nouveau_oclass *
-nv108_graph_oclass = &(struct nvc0_graph_oclass) {
+nv108_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0x08),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nv108_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = nv108_gr_fini,
 	},
 	.cclass = &nv108_grctx_oclass,
-	.sclass =  nv108_graph_sclass,
-	.mmio = nv108_graph_pack_mmio,
-	.fecs.ucode = &nv108_graph_fecs_ucode,
-	.gpccs.ucode = &nv108_graph_gpccs_ucode,
+	.sclass =  nv108_gr_sclass,
+	.mmio = nv108_gr_pack_mmio,
+	.fecs.ucode = &nv108_gr_fecs_ucode,
+	.gpccs.ucode = &nv108_gr_gpccs_ucode,
 	.ppc_nr = 1,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

@@ -7,7 +7,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/fifo.h>
 
 #include "nv20.h"
@@ -18,22 +18,22 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nv20_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
-	{ 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
-	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
+nv20_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
+	{ 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
+	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
+	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
 	{},
 };
 
@@ -42,15 +42,15 @@ nv20_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv20_graph_context_ctor(struct nouveau_object *parent,
+nv20_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv20_graph_chan *chan;
+	struct nv20_gr_chan *chan;
 	int ret, i;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
 					   0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
 					   &chan);
 	*pobject = nv_object(chan);
@@ -107,13 +107,13 @@ nv20_graph_context_ctor(struct nouveau_object *parent,
 }
 
 int
-nv20_graph_context_init(struct nouveau_object *object)
+nv20_gr_context_init(struct nouveau_object *object)
 {
-	struct nv20_graph_priv *priv = (void *)object->engine;
-	struct nv20_graph_chan *chan = (void *)object;
+	struct nv20_gr_priv *priv = (void *)object->engine;
+	struct nv20_gr_chan *chan = (void *)object;
 	int ret;
 
-	ret = nouveau_graph_context_init(&chan->base);
+	ret = nouveau_gr_context_init(&chan->base);
 	if (ret)
 		return ret;
 
@@ -122,10 +122,10 @@ nv20_graph_context_init(struct nouveau_object *object)
 }
 
 int
-nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv20_gr_context_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nv20_graph_priv *priv = (void *)object->engine;
-	struct nv20_graph_chan *chan = (void *)object;
+	struct nv20_gr_priv *priv = (void *)object->engine;
+	struct nv20_gr_chan *chan = (void *)object;
 	int chid = -1;
 
 	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
@@ -141,19 +141,19 @@ nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
 	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
 
 	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
-	return nouveau_graph_context_fini(&chan->base, suspend);
+	return nouveau_gr_context_fini(&chan->base, suspend);
 }
 
 static struct nouveau_oclass
-nv20_graph_cclass = {
+nv20_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x20),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv20_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv20_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = nv20_gr_context_init,
+		.fini = nv20_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -162,15 +162,15 @@ nv20_graph_cclass = {
  ******************************************************************************/
 
 void
-nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
+nv20_gr_tile_prog(struct nouveau_engine *engine, int i)
 {
 	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
 	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
-	struct nv20_graph_priv *priv = (void *)engine;
+	struct nv20_gr_priv *priv = (void *)engine;
 	unsigned long flags;
 
 	pfifo->pause(pfifo, &flags);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
 	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
@@ -193,12 +193,12 @@ nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
 }
 
 void
-nv20_graph_intr(struct nouveau_subdev *subdev)
+nv20_gr_intr(struct nouveau_subdev *subdev)
 {
 	struct nouveau_engine *engine = nv_engine(subdev);
 	struct nouveau_object *engctx;
 	struct nouveau_handle *handle;
-	struct nv20_graph_priv *priv = (void *)subdev;
+	struct nv20_gr_priv *priv = (void *)subdev;
 	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
 	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
 	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -225,11 +225,11 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
 
 	if (show) {
 		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv10_graph_intr_name, show);
+		nouveau_bitfield_print(nv10_gr_intr_name, show);
 		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
+		nouveau_bitfield_print(nv04_gr_nsource, nsource);
 		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+		nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
 		pr_cont("\n");
 		nv_error(priv,
 			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -241,14 +241,14 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv20_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv20_graph_priv *priv;
+	struct nv20_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -259,31 +259,31 @@ nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv20_graph_cclass;
-	nv_engine(priv)->sclass = nv20_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+	nv_subdev(priv)->intr = nv20_gr_intr;
+	nv_engine(priv)->cclass = &nv20_gr_cclass;
+	nv_engine(priv)->sclass = nv20_gr_sclass;
+	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
 void
-nv20_graph_dtor(struct nouveau_object *object)
+nv20_gr_dtor(struct nouveau_object *object)
 {
-	struct nv20_graph_priv *priv = (void *)object;
+	struct nv20_gr_priv *priv = (void *)object;
 	nouveau_gpuobj_ref(NULL, &priv->ctxtab);
-	nouveau_graph_destroy(&priv->base);
+	nouveau_gr_destroy(&priv->base);
 }
 
 int
-nv20_graph_init(struct nouveau_object *object)
+nv20_gr_init(struct nouveau_object *object)
 {
 	struct nouveau_engine *engine = nv_engine(object);
-	struct nv20_graph_priv *priv = (void *)engine;
+	struct nv20_gr_priv *priv = (void *)engine;
 	struct nouveau_fb *pfb = nouveau_fb(object);
 	u32 tmp, vramsz;
 	int ret, i;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -372,12 +372,12 @@ nv20_graph_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv20_graph_oclass = {
+nv20_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x20),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv20_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv20_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv20_gr_ctor,
+		.dtor = nv20_gr_dtor,
+		.init = nv20_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h

@@ -0,0 +1,31 @@
+#ifndef __NV20_GR_H__
+#define __NV20_GR_H__
+
+#include <core/enum.h>
+
+#include <engine/gr.h>
+#include <engine/fifo.h>
+
+struct nv20_gr_priv {
+	struct nouveau_gr base;
+	struct nouveau_gpuobj *ctxtab;
+};
+
+struct nv20_gr_chan {
+	struct nouveau_gr_chan base;
+	int chid;
+};
+
+extern struct nouveau_oclass nv25_gr_sclass[];
+int  nv20_gr_context_init(struct nouveau_object *);
+int  nv20_gr_context_fini(struct nouveau_object *, bool);
+
+void nv20_gr_tile_prog(struct nouveau_engine *, int);
+void nv20_gr_intr(struct nouveau_subdev *);
+
+void nv20_gr_dtor(struct nouveau_object *);
+int  nv20_gr_init(struct nouveau_object *);
+
+int  nv30_gr_init(struct nouveau_object *);
+
+#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c

@@ -5,7 +5,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "nv20.h"
 #include "regs.h"
@@ -15,22 +15,22 @@
  ******************************************************************************/
 
 struct nouveau_oclass
-nv25_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
-	{ 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0597, &nv04_graph_ofuncs, NULL }, /* kelvin */
+nv25_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
+	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
+	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+	{ 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */
 	{},
 };
 
@@ -39,15 +39,15 @@ nv25_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv25_graph_context_ctor(struct nouveau_object *parent,
+nv25_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv20_graph_chan *chan;
+	struct nv20_gr_chan *chan;
 	int ret, i;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x3724,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724,
 					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
@@ -112,15 +112,15 @@ nv25_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_oclass
-nv25_graph_cclass = {
+nv25_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x25),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv25_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv25_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = nv20_gr_context_init,
+		.fini = nv20_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -129,14 +129,14 @@ nv25_graph_cclass = {
  ******************************************************************************/
 
 static int
-nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv20_graph_priv *priv;
+	struct nv20_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -147,20 +147,20 @@ nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv25_graph_cclass;
-	nv_engine(priv)->sclass = nv25_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+	nv_subdev(priv)->intr = nv20_gr_intr;
+	nv_engine(priv)->cclass = &nv25_gr_cclass;
+	nv_engine(priv)->sclass = nv25_gr_sclass;
+	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
 struct nouveau_oclass
-nv25_graph_oclass = {
+nv25_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x25),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv25_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv20_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv25_gr_ctor,
+		.dtor = nv20_gr_dtor,
+		.init = nv20_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c

@@ -5,7 +5,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "nv20.h"
 #include "regs.h"
@@ -15,15 +15,15 @@
  ******************************************************************************/
 
 static int
-nv2a_graph_context_ctor(struct nouveau_object *parent,
+nv2a_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv20_graph_chan *chan;
+	struct nv20_gr_chan *chan;
 	int ret, i;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x36b0,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
 					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
@@ -79,15 +79,15 @@ nv2a_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_oclass
-nv2a_graph_cclass = {
+nv2a_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x2a),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv2a_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv2a_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = nv20_gr_context_init,
+		.fini = nv20_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -96,14 +96,14 @@ nv2a_graph_cclass = {
  ******************************************************************************/
 
 static int
-nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv2a_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv20_graph_priv *priv;
+	struct nv20_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -114,20 +114,20 @@ nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv2a_graph_cclass;
-	nv_engine(priv)->sclass = nv25_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+	nv_subdev(priv)->intr = nv20_gr_intr;
+	nv_engine(priv)->cclass = &nv2a_gr_cclass;
+	nv_engine(priv)->sclass = nv25_gr_sclass;
+	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
 struct nouveau_oclass
-nv2a_graph_oclass = {
+nv2a_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x2a),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv2a_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv20_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv2a_gr_ctor,
+		.dtor = nv20_gr_dtor,
+		.init = nv20_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c

@@ -5,7 +5,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "nv20.h"
 #include "regs.h"
@@ -15,24 +15,24 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nv30_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
-	{ 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
-	{ 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
-	{ 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
-	{ 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */
+nv30_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+	{ 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
+	{ 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
+	{ 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
+	{ 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
+	{ 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */
 	{},
 };
 
@@ -41,15 +41,15 @@ nv30_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv30_graph_context_ctor(struct nouveau_object *parent,
+nv30_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv20_graph_chan *chan;
+	struct nv20_gr_chan *chan;
 	int ret, i;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
 					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
@@ -113,15 +113,15 @@ nv30_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_oclass
-nv30_graph_cclass = {
+nv30_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x30),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv30_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv30_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = nv20_gr_context_init,
+		.fini = nv20_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -130,14 +130,14 @@ nv30_graph_cclass = {
  ******************************************************************************/
 
 static int
-nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv30_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv20_graph_priv *priv;
+	struct nv20_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -148,22 +148,22 @@ nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv30_graph_cclass;
-	nv_engine(priv)->sclass = nv30_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+	nv_subdev(priv)->intr = nv20_gr_intr;
+	nv_engine(priv)->cclass = &nv30_gr_cclass;
+	nv_engine(priv)->sclass = nv30_gr_sclass;
+	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
 int
-nv30_graph_init(struct nouveau_object *object)
+nv30_gr_init(struct nouveau_object *object)
 {
 	struct nouveau_engine *engine = nv_engine(object);
-	struct nv20_graph_priv *priv = (void *)engine;
+	struct nv20_gr_priv *priv = (void *)engine;
 	struct nouveau_fb *pfb = nouveau_fb(object);
 	int ret, i;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -226,12 +226,12 @@ nv30_graph_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv30_graph_oclass = {
+nv30_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x30),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv30_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv30_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv30_gr_ctor,
+		.dtor = nv20_gr_dtor,
+		.init = nv30_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c

@@ -5,7 +5,7 @@
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "nv20.h"
 #include "regs.h"
@@ -15,24 +15,24 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nv34_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
-	{ 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
-	{ 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
-	{ 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
-	{ 0x0697, &nv04_graph_ofuncs, NULL }, /* rankine */
+nv34_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+	{ 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
+	{ 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
+	{ 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
+	{ 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
+	{ 0x0697, &nv04_gr_ofuncs, NULL }, /* rankine */
 	{},
 };
 
@@ -41,15 +41,15 @@ nv34_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv34_graph_context_ctor(struct nouveau_object *parent,
+nv34_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv20_graph_chan *chan;
+	struct nv20_gr_chan *chan;
 	int ret, i;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x46dc,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
 					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
@@ -113,15 +113,15 @@ nv34_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_oclass
-nv34_graph_cclass = {
+nv34_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x34),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv34_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv34_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = nv20_gr_context_init,
+		.fini = nv20_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -130,14 +130,14 @@ nv34_graph_cclass = {
  ******************************************************************************/
 
 static int
-nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv34_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv20_graph_priv *priv;
+	struct nv20_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -148,20 +148,20 @@ nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv34_graph_cclass;
-	nv_engine(priv)->sclass = nv34_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+	nv_subdev(priv)->intr = nv20_gr_intr;
+	nv_engine(priv)->cclass = &nv34_gr_cclass;
+	nv_engine(priv)->sclass = nv34_gr_sclass;
+	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
 struct nouveau_oclass
-nv34_graph_oclass = {
+nv34_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x34),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv34_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv30_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv34_gr_ctor,
+		.dtor = nv20_gr_dtor,
+		.init = nv30_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c

@@ -13,24 +13,24 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nv35_graph_sclass[] = {
-	{ 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
-	{ 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
-	{ 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
-	{ 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
-	{ 0x0497, &nv04_graph_ofuncs, NULL }, /* rankine */
+nv35_gr_sclass[] = {
+	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+	{ 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
+	{ 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
+	{ 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
+	{ 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
+	{ 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */
 	{},
 };
 
@@ -39,15 +39,15 @@ nv35_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv35_graph_context_ctor(struct nouveau_object *parent,
+nv35_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv20_graph_chan *chan;
+	struct nv20_gr_chan *chan;
 	int ret, i;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x577c,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x577c,
 					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
@@ -111,15 +111,15 @@ nv35_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_oclass
-nv35_graph_cclass = {
+nv35_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x35),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv35_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = nv20_graph_context_init,
-		.fini = nv20_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv35_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = nv20_gr_context_init,
+		.fini = nv20_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -128,14 +128,14 @@ nv35_graph_cclass = {
  ******************************************************************************/
 
 static int
-nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv35_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv20_graph_priv *priv;
+	struct nv20_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -146,20 +146,20 @@ nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_graph_intr;
-	nv_engine(priv)->cclass = &nv35_graph_cclass;
-	nv_engine(priv)->sclass = nv35_graph_sclass;
-	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+	nv_subdev(priv)->intr = nv20_gr_intr;
+	nv_engine(priv)->cclass = &nv35_gr_cclass;
+	nv_engine(priv)->sclass = nv35_gr_sclass;
+	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
 struct nouveau_oclass
-nv35_graph_oclass = {
+nv35_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x35),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv35_graph_ctor,
-		.dtor = nv20_graph_dtor,
-		.init = nv30_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv35_gr_ctor,
+		.dtor = nv20_gr_dtor,
+		.init = nv30_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

@@ -30,25 +30,25 @@
 #include <subdev/fb.h>
 #include <subdev/timer.h>
 
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/fifo.h>
 
 #include "nv40.h"
 #include "regs.h"
 
-struct nv40_graph_priv {
-	struct nouveau_graph base;
+struct nv40_gr_priv {
+	struct nouveau_gr base;
 	u32 size;
 };
 
-struct nv40_graph_chan {
-	struct nouveau_graph_chan base;
+struct nv40_gr_chan {
+	struct nouveau_gr_chan base;
 };
 
 static u64
-nv40_graph_units(struct nouveau_graph *graph)
+nv40_gr_units(struct nouveau_gr *gr)
 {
-	struct nv40_graph_priv *priv = (void *)graph;
+	struct nv40_gr_priv *priv = (void *)gr;
 
 	return nv_rd32(priv, 0x1540);
 }
@@ -58,7 +58,7 @@ nv40_graph_units(struct nouveau_graph *graph)
  ******************************************************************************/
 
 static int
-nv40_graph_object_ctor(struct nouveau_object *parent,
+nv40_gr_object_ctor(struct nouveau_object *parent,
 		       struct nouveau_object *engine,
 		       struct nouveau_oclass *oclass, void *data, u32 size,
 		       struct nouveau_object **pobject)
@@ -84,8 +84,8 @@ nv40_graph_object_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_ofuncs
-nv40_graph_ofuncs = {
-	.ctor = nv40_graph_object_ctor,
+nv40_gr_ofuncs = {
+	.ctor = nv40_gr_object_ctor,
 	.dtor = _nouveau_gpuobj_dtor,
 	.init = _nouveau_gpuobj_init,
 	.fini = _nouveau_gpuobj_fini,
@@ -94,44 +94,44 @@ nv40_graph_ofuncs = {
 };
 
 static struct nouveau_oclass
-nv40_graph_sclass[] = {
-	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
-	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
-	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
-	{ 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
+nv40_gr_sclass[] = {
+	{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv40_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */
+	{ 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */
+	{ 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */
+	{ 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */
+	{ 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */
+	{ 0x4097, &nv40_gr_ofuncs, NULL }, /* curie */
 	{},
 };
 
 static struct nouveau_oclass
-nv44_graph_sclass[] = {
-	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
-	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
-	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
-	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
-	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
-	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
-	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
-	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
-	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
-	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
-	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
-	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
-	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
-	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
-	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
-	{ 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
+nv44_gr_sclass[] = {
+	{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
+	{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
+	{ 0x0030, &nv40_gr_ofuncs, NULL }, /* null */
+	{ 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */
+	{ 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */
+	{ 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */
+	{ 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */
+	{ 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */
+	{ 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */
+	{ 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */
+	{ 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */
+	{ 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */
+	{ 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */
+	{ 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */
+	{ 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */
+	{ 0x4497, &nv40_gr_ofuncs, NULL }, /* curie */
 	{},
 };
 
@@ -140,16 +140,16 @@ nv44_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv40_graph_context_ctor(struct nouveau_object *parent,
+nv40_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv40_graph_priv *priv = (void *)engine;
-	struct nv40_graph_chan *chan;
+	struct nv40_gr_priv *priv = (void *)engine;
+	struct nv40_gr_chan *chan;
 	int ret;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
 					   priv->size, 16,
 					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
@@ -162,10 +162,10 @@ nv40_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static int
-nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv40_gr_context_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nv40_graph_priv *priv = (void *)object->engine;
-	struct nv40_graph_chan *chan = (void *)object;
+	struct nv40_gr_priv *priv = (void *)object->engine;
+	struct nv40_gr_chan *chan = (void *)object;
 	u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
 	int ret = 0;
 
@@ -195,15 +195,15 @@ nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
 }
 
 static struct nouveau_oclass
-nv40_graph_cclass = {
+nv40_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x40),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = nv40_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv40_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = nv40_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -212,15 +212,15 @@ nv40_graph_cclass = {
  ******************************************************************************/
 
 static void
-nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
+nv40_gr_tile_prog(struct nouveau_engine *engine, int i)
 {
 	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
 	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
-	struct nv40_graph_priv *priv = (void *)engine;
+	struct nv40_gr_priv *priv = (void *)engine;
 	unsigned long flags;
 
 	pfifo->pause(pfifo, &flags);
-	nv04_graph_idle(priv);
+	nv04_gr_idle(priv);
 
 	switch (nv_device(priv)->chipset) {
 	case 0x40:
@@ -290,13 +290,13 @@ nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
 }
 
 static void
-nv40_graph_intr(struct nouveau_subdev *subdev)
+nv40_gr_intr(struct nouveau_subdev *subdev)
 {
 	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 	struct nouveau_engine *engine = nv_engine(subdev);
 	struct nouveau_object *engctx;
 	struct nouveau_handle *handle = NULL;
-	struct nv40_graph_priv *priv = (void *)subdev;
+	struct nv40_gr_priv *priv = (void *)subdev;
 	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
 	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
 	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -330,11 +330,11 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
 
 	if (show) {
 		nv_error(priv, "%s", "");
-		nouveau_bitfield_print(nv10_graph_intr_name, show);
+		nouveau_bitfield_print(nv10_gr_intr_name, show);
 		pr_cont(" nsource:");
-		nouveau_bitfield_print(nv04_graph_nsource, nsource);
+		nouveau_bitfield_print(nv04_gr_nsource, nsource);
 		pr_cont(" nstatus:");
-		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+		nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
 		pr_cont("\n");
 		nv_error(priv,
 			 "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -346,41 +346,41 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv40_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv40_graph_priv *priv;
+	struct nv40_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv40_graph_intr;
-	nv_engine(priv)->cclass = &nv40_graph_cclass;
-	if (nv44_graph_class(priv))
-		nv_engine(priv)->sclass = nv44_graph_sclass;
+	nv_subdev(priv)->intr = nv40_gr_intr;
+	nv_engine(priv)->cclass = &nv40_gr_cclass;
+	if (nv44_gr_class(priv))
+		nv_engine(priv)->sclass = nv44_gr_sclass;
 	else
-		nv_engine(priv)->sclass = nv40_graph_sclass;
-	nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
+		nv_engine(priv)->sclass = nv40_gr_sclass;
+	nv_engine(priv)->tile_prog = nv40_gr_tile_prog;
 
-	priv->base.units = nv40_graph_units;
+	priv->base.units = nv40_gr_units;
 	return 0;
 }
 
 static int
-nv40_graph_init(struct nouveau_object *object)
+nv40_gr_init(struct nouveau_object *object)
 {
 	struct nouveau_engine *engine = nv_engine(object);
 	struct nouveau_fb *pfb = nouveau_fb(object);
-	struct nv40_graph_priv *priv = (void *)engine;
+	struct nv40_gr_priv *priv = (void *)engine;
 	int ret, i, j;
 	u32 vramsz;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -525,12 +525,12 @@ nv40_graph_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv40_graph_oclass = {
+nv40_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x40),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv40_graph_ctor,
-		.dtor = _nouveau_graph_dtor,
-		.init = nv40_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv40_gr_ctor,
+		.dtor = _nouveau_gr_dtor,
+		.init = nv40_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h

@@ -1,5 +1,5 @@
-#ifndef __NV40_GRAPH_H__
-#define __NV40_GRAPH_H__
+#ifndef __NV40_GR_H__
+#define __NV40_GR_H__
 
 #include <core/device.h>
 #include <core/gpuobj.h>
@@ -8,7 +8,7 @@
  * helpful to determine a number of other hardware features
  */
 static inline int
-nv44_graph_class(void *priv)
+nv44_gr_class(void *priv)
 {
 	struct nouveau_device *device = nv_device(priv);
 

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

@@ -33,24 +33,24 @@
 #include <subdev/timer.h>
 
 #include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 
 #include "nv50.h"
 
-struct nv50_graph_priv {
-	struct nouveau_graph base;
+struct nv50_gr_priv {
+	struct nouveau_gr base;
 	spinlock_t lock;
 	u32 size;
 };
 
-struct nv50_graph_chan {
-	struct nouveau_graph_chan base;
+struct nv50_gr_chan {
+	struct nouveau_gr_chan base;
 };
 
 static u64
-nv50_graph_units(struct nouveau_graph *graph)
+nv50_gr_units(struct nouveau_gr *gr)
 {
-	struct nv50_graph_priv *priv = (void *)graph;
+	struct nv50_gr_priv *priv = (void *)gr;
 
 	return nv_rd32(priv, 0x1540);
 }
@@ -60,7 +60,7 @@ nv50_graph_units(struct nouveau_graph *graph)
  ******************************************************************************/
 
 static int
-nv50_graph_object_ctor(struct nouveau_object *parent,
+nv50_gr_object_ctor(struct nouveau_object *parent,
 		       struct nouveau_object *engine,
 		       struct nouveau_oclass *oclass, void *data, u32 size,
 		       struct nouveau_object **pobject)
@@ -82,8 +82,8 @@ nv50_graph_object_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_ofuncs
-nv50_graph_ofuncs = {
-	.ctor = nv50_graph_object_ctor,
+nv50_gr_ofuncs = {
+	.ctor = nv50_gr_object_ctor,
 	.dtor = _nouveau_gpuobj_dtor,
 	.init = _nouveau_gpuobj_init,
 	.fini = _nouveau_gpuobj_fini,
@@ -92,54 +92,54 @@ nv50_graph_ofuncs = {
 };
 
 static struct nouveau_oclass
-nv50_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x5097, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
+nv50_gr_sclass[] = {
+	{ 0x0030, &nv50_gr_ofuncs },
+	{ 0x502d, &nv50_gr_ofuncs },
+	{ 0x5039, &nv50_gr_ofuncs },
+	{ 0x5097, &nv50_gr_ofuncs },
+	{ 0x50c0, &nv50_gr_ofuncs },
 	{}
 };
 
 static struct nouveau_oclass
-nv84_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x8297, &nv50_graph_ofuncs },
+nv84_gr_sclass[] = {
+	{ 0x0030, &nv50_gr_ofuncs },
+	{ 0x502d, &nv50_gr_ofuncs },
+	{ 0x5039, &nv50_gr_ofuncs },
+	{ 0x50c0, &nv50_gr_ofuncs },
+	{ 0x8297, &nv50_gr_ofuncs },
 	{}
 };
 
 static struct nouveau_oclass
-nva0_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x8397, &nv50_graph_ofuncs },
+nva0_gr_sclass[] = {
+	{ 0x0030, &nv50_gr_ofuncs },
+	{ 0x502d, &nv50_gr_ofuncs },
+	{ 0x5039, &nv50_gr_ofuncs },
+	{ 0x50c0, &nv50_gr_ofuncs },
+	{ 0x8397, &nv50_gr_ofuncs },
 	{}
 };
 
 static struct nouveau_oclass
-nva3_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x8597, &nv50_graph_ofuncs },
-	{ 0x85c0, &nv50_graph_ofuncs },
+nva3_gr_sclass[] = {
+	{ 0x0030, &nv50_gr_ofuncs },
+	{ 0x502d, &nv50_gr_ofuncs },
+	{ 0x5039, &nv50_gr_ofuncs },
+	{ 0x50c0, &nv50_gr_ofuncs },
+	{ 0x8597, &nv50_gr_ofuncs },
+	{ 0x85c0, &nv50_gr_ofuncs },
 	{}
 };
 
 static struct nouveau_oclass
-nvaf_graph_sclass[] = {
-	{ 0x0030, &nv50_graph_ofuncs },
-	{ 0x502d, &nv50_graph_ofuncs },
-	{ 0x5039, &nv50_graph_ofuncs },
-	{ 0x50c0, &nv50_graph_ofuncs },
-	{ 0x85c0, &nv50_graph_ofuncs },
-	{ 0x8697, &nv50_graph_ofuncs },
+nvaf_gr_sclass[] = {
+	{ 0x0030, &nv50_gr_ofuncs },
+	{ 0x502d, &nv50_gr_ofuncs },
+	{ 0x5039, &nv50_gr_ofuncs },
+	{ 0x50c0, &nv50_gr_ofuncs },
+	{ 0x85c0, &nv50_gr_ofuncs },
+	{ 0x8697, &nv50_gr_ofuncs },
 	{}
 };
 
@@ -148,16 +148,16 @@ nvaf_graph_sclass[] = {
  ******************************************************************************/
 
 static int
-nv50_graph_context_ctor(struct nouveau_object *parent,
+nv50_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *data, u32 size,
 			struct nouveau_object **pobject)
 {
-	struct nv50_graph_priv *priv = (void *)engine;
-	struct nv50_graph_chan *chan;
+	struct nv50_gr_priv *priv = (void *)engine;
+	struct nv50_gr_chan *chan;
 	int ret;
 
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
 					   priv->size, 0,
 					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
@@ -169,15 +169,15 @@ nv50_graph_context_ctor(struct nouveau_object *parent,
 }
 
 static struct nouveau_oclass
-nv50_graph_cclass = {
+nv50_gr_cclass = {
 	.handle = NV_ENGCTX(GR, 0x50),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_graph_context_ctor,
-		.dtor = _nouveau_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nv50_gr_context_ctor,
+		.dtor = _nouveau_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 };
 
@@ -185,7 +185,7 @@ nv50_graph_cclass = {
  * PGRAPH engine/subdev functions
  ******************************************************************************/
 
-static const struct nouveau_bitfield nv50_pgraph_status[] = {
+static const struct nouveau_bitfield nv50_pgr_status[] = {
 	{ 0x00000001, "BUSY" }, /* set when any bit is set */
 	{ 0x00000002, "DISPATCH" },
 	{ 0x00000004, "UNK2" },
@@ -214,21 +214,21 @@ static const struct nouveau_bitfield nv50_pgraph_status[] = {
 	{}
 };
 
-static const char *const nv50_pgraph_vstatus_0[] = {
+static const char *const nv50_pgr_vstatus_0[] = {
 	"VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
 	NULL
 };
 
-static const char *const nv50_pgraph_vstatus_1[] = {
+static const char *const nv50_pgr_vstatus_1[] = {
 	"TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
 };
 
-static const char *const nv50_pgraph_vstatus_2[] = {
+static const char *const nv50_pgr_vstatus_2[] = {
 	"RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
 	"ROP", NULL
 };
 
-static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
+static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
 		const char *const units[], u32 status)
 {
 	int i;
@@ -246,10 +246,10 @@ static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
 }
 
 static int
-nv84_graph_tlb_flush(struct nouveau_engine *engine)
+nv84_gr_tlb_flush(struct nouveau_engine *engine)
 {
 	struct nouveau_timer *ptimer = nouveau_timer(engine);
-	struct nv50_graph_priv *priv = (void *)engine;
+	struct nv50_gr_priv *priv = (void *)engine;
 	bool idle, timeout = false;
 	unsigned long flags;
 	u64 start;
@@ -284,14 +284,14 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
 
 		tmp = nv_rd32(priv, 0x400700);
 		nv_error(priv, "PGRAPH_STATUS  : 0x%08x", tmp);
-		nouveau_bitfield_print(nv50_pgraph_status, tmp);
+		nouveau_bitfield_print(nv50_pgr_status, tmp);
 		pr_cont("\n");
 
-		nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
+		nouveau_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
 				nv_rd32(priv, 0x400380));
-		nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
+		nouveau_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
 				nv_rd32(priv, 0x400384));
-		nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
+		nouveau_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
 				nv_rd32(priv, 0x400388));
 	}
 
@@ -338,24 +338,24 @@ static const struct nouveau_bitfield nv50_tex_traps[] = {
 	{}
 };
 
-static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
+static const struct nouveau_bitfield nv50_gr_trap_m2mf[] = {
 	{ 0x00000001, "NOTIFY" },
 	{ 0x00000002, "IN" },
 	{ 0x00000004, "OUT" },
 	{}
 };
 
-static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
+static const struct nouveau_bitfield nv50_gr_trap_vfetch[] = {
 	{ 0x00000001, "FAULT" },
 	{}
 };
 
-static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
+static const struct nouveau_bitfield nv50_gr_trap_strmout[] = {
 	{ 0x00000001, "FAULT" },
 	{}
 };
 
-static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
+static const struct nouveau_bitfield nv50_gr_trap_ccache[] = {
 	{ 0x00000001, "FAULT" },
 	{}
 };
@@ -407,7 +407,7 @@ const struct nouveau_enum nv50_data_error_names[] = {
 	{}
 };
 
-static const struct nouveau_bitfield nv50_graph_intr_name[] = {
+static const struct nouveau_bitfield nv50_gr_intr_name[] = {
 	{ 0x00000001, "NOTIFY" },
 	{ 0x00000002, "COMPUTE_QUERY" },
 	{ 0x00000010, "ILLEGAL_MTHD" },
@@ -421,7 +421,7 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = {
 	{}
 };
 
-static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
+static const struct nouveau_bitfield nv50_gr_trap_prop[] = {
 	{ 0x00000004, "SURF_WIDTH_OVERRUN" },
 	{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
 	{ 0x00000010, "DST2D_FAULT" },
@@ -437,7 +437,7 @@ static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
 };
 
 static void
-nv50_priv_prop_trap(struct nv50_graph_priv *priv,
+nv50_priv_prop_trap(struct nv50_gr_priv *priv,
 		    u32 ustatus_addr, u32 ustatus, u32 tp)
 {
 	u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
@@ -468,7 +468,7 @@ nv50_priv_prop_trap(struct nv50_graph_priv *priv,
 	}
 	if (ustatus) {
 		nv_error(priv, "TRAP_PROP - TP %d -", tp);
-		nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
+		nouveau_bitfield_print(nv50_gr_trap_prop, ustatus);
 		pr_cont(" - Address %02x%08x\n", e14, e10);
 	}
 	nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
@@ -476,7 +476,7 @@ nv50_priv_prop_trap(struct nv50_graph_priv *priv,
 }
 
 static void
-nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
+nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display)
 {
 	u32 units = nv_rd32(priv, 0x1540);
 	u32 addr, mp10, status, pc, oplow, ophigh;
@@ -515,7 +515,7 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
 }
 
 static void
-nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
+nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
 		u32 ustatus_new, int display, const char *name)
 {
 	int tps = 0;
@@ -580,7 +580,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
 }
 
 static int
-nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
+nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
 			int chid, u64 inst, struct nouveau_object *engctx)
 {
 	u32 status = nv_rd32(priv, 0x400108);
@@ -670,7 +670,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
 		u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
 		if (display) {
 			nv_error(priv, "TRAP_M2MF");
-			nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
+			nouveau_bitfield_print(nv50_gr_trap_m2mf, ustatus);
 			pr_cont("\n");
 			nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
 				nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
@@ -691,7 +691,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
 		u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
 		if (display) {
 			nv_error(priv, "TRAP_VFETCH");
-			nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
+			nouveau_bitfield_print(nv50_gr_trap_vfetch, ustatus);
 			pr_cont("\n");
 			nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
 				nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
@@ -708,7 +708,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
 		ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
 		if (display) {
 			nv_error(priv, "TRAP_STRMOUT");
-			nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
+			nouveau_bitfield_print(nv50_gr_trap_strmout, ustatus);
 			pr_cont("\n");
 			nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
 				nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
@@ -729,7 +729,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
 		ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
 		if (display) {
 			nv_error(priv, "TRAP_CCACHE");
-			nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
+			nouveau_bitfield_print(nv50_gr_trap_ccache, ustatus);
 			pr_cont("\n");
 			nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
 				     " %08x %08x %08x\n",
@@ -791,13 +791,13 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
 }
 
 static void
-nv50_graph_intr(struct nouveau_subdev *subdev)
+nv50_gr_intr(struct nouveau_subdev *subdev)
 {
 	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 	struct nouveau_engine *engine = nv_engine(subdev);
 	struct nouveau_object *engctx;
 	struct nouveau_handle *handle = NULL;
-	struct nv50_graph_priv *priv = (void *)subdev;
+	struct nv50_gr_priv *priv = (void *)subdev;
 	u32 stat = nv_rd32(priv, 0x400100);
 	u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
 	u32 addr = nv_rd32(priv, 0x400704);
@@ -827,7 +827,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
 	}
 
 	if (stat & 0x00200000) {
-		if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
+		if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12,
 				engctx))
 			show &= ~0x00200000;
 		show_bitfield &= ~0x00200000;
@@ -840,7 +840,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
 		show &= show_bitfield;
 		if (show) {
 			nv_error(priv, "%s", "");
-			nouveau_bitfield_print(nv50_graph_intr_name, show);
+			nouveau_bitfield_print(nv50_gr_intr_name, show);
 			pr_cont("\n");
 		}
 		nv_error(priv,
@@ -856,27 +856,27 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	       struct nouveau_oclass *oclass, void *data, u32 size,
 	       struct nouveau_object **pobject)
 {
-	struct nv50_graph_priv *priv;
+	struct nv50_gr_priv *priv;
 	int ret;
 
-	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00201000;
-	nv_subdev(priv)->intr = nv50_graph_intr;
-	nv_engine(priv)->cclass = &nv50_graph_cclass;
+	nv_subdev(priv)->intr = nv50_gr_intr;
+	nv_engine(priv)->cclass = &nv50_gr_cclass;
 
-	priv->base.units = nv50_graph_units;
+	priv->base.units = nv50_gr_units;
 
 	switch (nv_device(priv)->chipset) {
 	case 0x50:
-		nv_engine(priv)->sclass = nv50_graph_sclass;
+		nv_engine(priv)->sclass = nv50_gr_sclass;
 		break;
 	case 0x84:
 	case 0x86:
@@ -884,20 +884,20 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	case 0x94:
 	case 0x96:
 	case 0x98:
-		nv_engine(priv)->sclass = nv84_graph_sclass;
+		nv_engine(priv)->sclass = nv84_gr_sclass;
 		break;
 	case 0xa0:
 	case 0xaa:
 	case 0xac:
-		nv_engine(priv)->sclass = nva0_graph_sclass;
+		nv_engine(priv)->sclass = nva0_gr_sclass;
 		break;
 	case 0xa3:
 	case 0xa5:
 	case 0xa8:
-		nv_engine(priv)->sclass = nva3_graph_sclass;
+		nv_engine(priv)->sclass = nva3_gr_sclass;
 		break;
 	case 0xaf:
-		nv_engine(priv)->sclass = nvaf_graph_sclass;
+		nv_engine(priv)->sclass = nvaf_gr_sclass;
 		break;
 
 	}
@@ -905,19 +905,19 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	/* unfortunate hw bug workaround... */
 	if (nv_device(priv)->chipset != 0x50 &&
 	    nv_device(priv)->chipset != 0xac)
-		nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
+		nv_engine(priv)->tlb_flush = nv84_gr_tlb_flush;
 
 	spin_lock_init(&priv->lock);
 	return 0;
 }
 
 static int
-nv50_graph_init(struct nouveau_object *object)
+nv50_gr_init(struct nouveau_object *object)
 {
-	struct nv50_graph_priv *priv = (void *)object;
+	struct nv50_gr_priv *priv = (void *)object;
 	int ret, units, i;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -998,12 +998,12 @@ nv50_graph_init(struct nouveau_object *object)
 }
 
 struct nouveau_oclass
-nv50_graph_oclass = {
+nv50_gr_oclass = {
 	.handle = NV_ENGINE(GR, 0x50),
 	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv50_graph_ctor,
-		.dtor = _nouveau_graph_dtor,
-		.init = nv50_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nv50_gr_ctor,
+		.dtor = _nouveau_gr_dtor,
+		.init = nv50_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h

@@ -1,5 +1,5 @@
-#ifndef __NV50_GRAPH_H__
-#define __NV50_GRAPH_H__
+#ifndef __NV50_GR_H__
+#define __NV50_GR_H__
 
 int  nv50_grctx_init(struct nouveau_device *, u32 *size);
 void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c

@@ -30,7 +30,7 @@
  ******************************************************************************/
 
 static void
-nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc)
+nvc0_gr_zbc_clear_color(struct nvc0_gr_priv *priv, int zbc)
 {
 	if (priv->zbc_color[zbc].format) {
 		nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
@@ -44,7 +44,7 @@ nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc)
 }
 
 static int
-nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format,
+nvc0_gr_zbc_color_get(struct nvc0_gr_priv *priv, int format,
 			 const u32 ds[4], const u32 l2[4])
 {
 	struct nouveau_ltc *ltc = nouveau_ltc(priv);
@@ -75,12 +75,12 @@ nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format,
 	memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
 	priv->zbc_color[zbc].format = format;
 	ltc->zbc_color_get(ltc, zbc, l2);
-	nvc0_graph_zbc_clear_color(priv, zbc);
+	nvc0_gr_zbc_clear_color(priv, zbc);
 	return zbc;
 }
 
 static void
-nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc)
+nvc0_gr_zbc_clear_depth(struct nvc0_gr_priv *priv, int zbc)
 {
 	if (priv->zbc_depth[zbc].format)
 		nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
@@ -90,7 +90,7 @@ nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc)
 }
 
 static int
-nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
+nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format,
 			 const u32 ds, const u32 l2)
 {
 	struct nouveau_ltc *ltc = nouveau_ltc(priv);
@@ -119,7 +119,7 @@ nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
 	priv->zbc_depth[zbc].ds = ds;
 	priv->zbc_depth[zbc].l2 = l2;
 	ltc->zbc_depth_get(ltc, zbc, l2);
-	nvc0_graph_zbc_clear_depth(priv, zbc);
+	nvc0_gr_zbc_clear_depth(priv, zbc);
 	return zbc;
 }
 
@@ -130,7 +130,7 @@ nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
 static int
 nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
 {
-	struct nvc0_graph_priv *priv = (void *)object->engine;
+	struct nvc0_gr_priv *priv = (void *)object->engine;
 	union {
 		struct fermi_a_zbc_color_v0 v0;
 	} *args = data;
@@ -157,7 +157,7 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
 		case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
 		case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
 		case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
-			ret = nvc0_graph_zbc_color_get(priv, args->v0.format,
+			ret = nvc0_gr_zbc_color_get(priv, args->v0.format,
 							     args->v0.ds,
 							     args->v0.l2);
 			if (ret >= 0) {
@@ -176,7 +176,7 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
 static int
 nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
 {
-	struct nvc0_graph_priv *priv = (void *)object->engine;
+	struct nvc0_gr_priv *priv = (void *)object->engine;
 	union {
 		struct fermi_a_zbc_depth_v0 v0;
 	} *args = data;
@@ -185,7 +185,7 @@ nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
 	if (nvif_unpack(args->v0, 0, 0, false)) {
 		switch (args->v0.format) {
 		case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
-			ret = nvc0_graph_zbc_depth_get(priv, args->v0.format,
+			ret = nvc0_gr_zbc_depth_get(priv, args->v0.format,
 							     args->v0.ds,
 							     args->v0.l2);
 			return (ret >= 0) ? 0 : -ENOSPC;
@@ -221,10 +221,10 @@ nvc0_fermi_ofuncs = {
 };
 
 static int
-nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
+nvc0_gr_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
 				 void *pdata, u32 size)
 {
-	struct nvc0_graph_priv *priv = (void *)nv_engine(object);
+	struct nvc0_gr_priv *priv = (void *)nv_engine(object);
 	if (size >= sizeof(u32)) {
 		u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
 		nv_wr32(priv, 0x419e44, data);
@@ -235,23 +235,23 @@ nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
 }
 
 struct nouveau_omthds
-nvc0_graph_9097_omthds[] = {
-	{ 0x1528, 0x1528, nvc0_graph_set_shader_exceptions },
+nvc0_gr_9097_omthds[] = {
+	{ 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
 	{}
 };
 
 struct nouveau_omthds
-nvc0_graph_90c0_omthds[] = {
-	{ 0x1528, 0x1528, nvc0_graph_set_shader_exceptions },
+nvc0_gr_90c0_omthds[] = {
+	{ 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
 	{}
 };
 
 struct nouveau_oclass
-nvc0_graph_sclass[] = {
+nvc0_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0x9039, &nouveau_object_ofuncs },
-	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
@@ -260,20 +260,20 @@ nvc0_graph_sclass[] = {
  ******************************************************************************/
 
 int
-nvc0_graph_context_ctor(struct nouveau_object *parent,
+nvc0_gr_context_ctor(struct nouveau_object *parent,
 			struct nouveau_object *engine,
 			struct nouveau_oclass *oclass, void *args, u32 size,
 			struct nouveau_object **pobject)
 {
 	struct nouveau_vm *vm = nouveau_client(parent)->vm;
-	struct nvc0_graph_priv *priv = (void *)engine;
-	struct nvc0_graph_data *data = priv->mmio_data;
-	struct nvc0_graph_mmio *mmio = priv->mmio_list;
-	struct nvc0_graph_chan *chan;
+	struct nvc0_gr_priv *priv = (void *)engine;
+	struct nvc0_gr_data *data = priv->mmio_data;
+	struct nvc0_gr_mmio *mmio = priv->mmio_list;
+	struct nvc0_gr_chan *chan;
 	int ret, i;
 
 	/* allocate memory for context, and fill with default values */
-	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+	ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
 					   priv->size, 0x100,
 					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
 	*pobject = nv_object(chan);
@@ -347,9 +347,9 @@ nvc0_graph_context_ctor(struct nouveau_object *parent,
 }
 
 void
-nvc0_graph_context_dtor(struct nouveau_object *object)
+nvc0_gr_context_dtor(struct nouveau_object *object)
 {
-	struct nvc0_graph_chan *chan = (void *)object;
+	struct nvc0_gr_chan *chan = (void *)object;
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
@@ -360,15 +360,15 @@ nvc0_graph_context_dtor(struct nouveau_object *object)
 	nouveau_gpuobj_unmap(&chan->mmio_vma);
 	nouveau_gpuobj_ref(NULL, &chan->mmio);
 
-	nouveau_graph_context_destroy(&chan->base);
+	nouveau_gr_context_destroy(&chan->base);
 }
 
 /*******************************************************************************
  * PGRAPH register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
-nvc0_graph_init_main_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_main_0[] = {
 	{ 0x400080,   1, 0x04, 0x003083c2 },
 	{ 0x400088,   1, 0x04, 0x00006fe7 },
 	{ 0x40008c,   1, 0x04, 0x00000000 },
@@ -383,53 +383,53 @@ nvc0_graph_init_main_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_fe_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_fe_0[] = {
 	{ 0x40415c,   1, 0x04, 0x00000000 },
 	{ 0x404170,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_pri_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pri_0[] = {
 	{ 0x404488,   2, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_rstr2d_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_rstr2d_0[] = {
 	{ 0x407808,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_pd_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pd_0[] = {
 	{ 0x406024,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405908,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_scc_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_scc_0[] = {
 	{ 0x40803c,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_prop_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_prop_0[] = {
 	{ 0x4184a0,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_gpc_unk_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gpc_unk_0[] = {
 	{ 0x418604,   1, 0x04, 0x00000000 },
 	{ 0x418680,   1, 0x04, 0x00000000 },
 	{ 0x418714,   1, 0x04, 0x80000000 },
@@ -437,20 +437,20 @@ nvc0_graph_init_gpc_unk_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_setup_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_setup_0[] = {
 	{ 0x418814,   3, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_crstr_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_crstr_0[] = {
 	{ 0x418b04,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_setup_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_setup_1[] = {
 	{ 0x4188c8,   1, 0x04, 0x80000000 },
 	{ 0x4188cc,   1, 0x04, 0x00000000 },
 	{ 0x4188d0,   1, 0x04, 0x00010000 },
@@ -458,8 +458,8 @@ nvc0_graph_init_setup_1[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_zcull_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_zcull_0[] = {
 	{ 0x418910,   1, 0x04, 0x00010001 },
 	{ 0x418914,   1, 0x04, 0x00000301 },
 	{ 0x418918,   1, 0x04, 0x00800000 },
@@ -468,15 +468,15 @@ nvc0_graph_init_zcull_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_gpm_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gpm_0[] = {
 	{ 0x418c04,   1, 0x04, 0x00000000 },
 	{ 0x418c88,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_gpc_unk_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gpc_unk_1[] = {
 	{ 0x418d00,   1, 0x04, 0x00000000 },
 	{ 0x418f08,   1, 0x04, 0x00000000 },
 	{ 0x418e00,   1, 0x04, 0x00000050 },
@@ -484,30 +484,30 @@ nvc0_graph_init_gpc_unk_1[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_gcc_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gcc_0[] = {
 	{ 0x41900c,   1, 0x04, 0x00000000 },
 	{ 0x419018,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_tpccs_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_tpccs_0[] = {
 	{ 0x419d08,   2, 0x04, 0x00000000 },
 	{ 0x419d10,   1, 0x04, 0x00000014 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_tex_0[] = {
 	{ 0x419ab0,   1, 0x04, 0x00000000 },
 	{ 0x419ab8,   1, 0x04, 0x000000e7 },
 	{ 0x419abc,   2, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_pe_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pe_0[] = {
 	{ 0x41980c,   3, 0x04, 0x00000000 },
 	{ 0x419844,   1, 0x04, 0x00000000 },
 	{ 0x41984c,   1, 0x04, 0x00005bc5 },
@@ -515,8 +515,8 @@ nvc0_graph_init_pe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_l1c_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419ca8,   1, 0x04, 0x80000000 },
 	{ 0x419cb4,   1, 0x04, 0x00000000 },
@@ -526,27 +526,27 @@ nvc0_graph_init_l1c_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_wwdx_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_wwdx_0[] = {
 	{ 0x419bd4,   1, 0x04, 0x00800000 },
 	{ 0x419bdc,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_tpccs_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_tpccs_1[] = {
 	{ 0x419d2c,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_mpc_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_mpc_0[] = {
 	{ 0x419c0c,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-nvc0_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+nvc0_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000000 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ea4,   1, 0x04, 0x00000100 },
@@ -563,8 +563,8 @@ nvc0_graph_init_sm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_be_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_be_0[] = {
 	{ 0x40880c,   1, 0x04, 0x00000000 },
 	{ 0x408910,   9, 0x04, 0x00000000 },
 	{ 0x408950,   1, 0x04, 0x00000000 },
@@ -575,47 +575,47 @@ nvc0_graph_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_fe_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_fe_1[] = {
 	{ 0x4040f0,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvc0_graph_init_pe_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pe_1[] = {
 	{ 0x419880,   1, 0x04, 0x00000002 },
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvc0_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc0_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc0_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc0_graph_init_tex_0 },
-	{ nvc0_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc0_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{ nvc0_graph_init_pe_1 },
+static const struct nvc0_gr_pack
+nvc0_gr_pack_mmio[] = {
+	{ nvc0_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvc0_gr_init_pd_0 },
+	{ nvc0_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvc0_gr_init_prop_0 },
+	{ nvc0_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc0_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvc0_gr_init_gpm_0 },
+	{ nvc0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nvc0_gr_init_tpccs_0 },
+	{ nvc0_gr_init_tex_0 },
+	{ nvc0_gr_init_pe_0 },
+	{ nvc0_gr_init_l1c_0 },
+	{ nvc0_gr_init_wwdx_0 },
+	{ nvc0_gr_init_tpccs_1 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvc0_gr_init_sm_0 },
+	{ nvc0_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
+	{ nvc0_gr_init_pe_1 },
 	{}
 };
 
@@ -624,7 +624,7 @@ nvc0_graph_pack_mmio[] = {
  ******************************************************************************/
 
 void
-nvc0_graph_zbc_init(struct nvc0_graph_priv *priv)
+nvc0_gr_zbc_init(struct nvc0_gr_priv *priv)
 {
 	const u32  zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 			      0x00000000, 0x00000000, 0x00000000, 0x00000000 };
@@ -638,25 +638,25 @@ nvc0_graph_zbc_init(struct nvc0_graph_priv *priv)
 	int index;
 
 	if (!priv->zbc_color[0].format) {
-		nvc0_graph_zbc_color_get(priv, 1,  & zero[0],   &zero[4]);
-		nvc0_graph_zbc_color_get(priv, 2,  &  one[0],    &one[4]);
-		nvc0_graph_zbc_color_get(priv, 4,  &f32_0[0],  &f32_0[4]);
-		nvc0_graph_zbc_color_get(priv, 4,  &f32_1[0],  &f32_1[4]);
-		nvc0_graph_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
-		nvc0_graph_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
+		nvc0_gr_zbc_color_get(priv, 1,  & zero[0],   &zero[4]);
+		nvc0_gr_zbc_color_get(priv, 2,  &  one[0],    &one[4]);
+		nvc0_gr_zbc_color_get(priv, 4,  &f32_0[0],  &f32_0[4]);
+		nvc0_gr_zbc_color_get(priv, 4,  &f32_1[0],  &f32_1[4]);
+		nvc0_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
+		nvc0_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
 	}
 
 	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
-		nvc0_graph_zbc_clear_color(priv, index);
+		nvc0_gr_zbc_clear_color(priv, index);
 	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
-		nvc0_graph_zbc_clear_depth(priv, index);
+		nvc0_gr_zbc_clear_depth(priv, index);
 }
 
 void
-nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
+nvc0_gr_mmio(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
 {
-	const struct nvc0_graph_pack *pack;
-	const struct nvc0_graph_init *init;
+	const struct nvc0_gr_pack *pack;
+	const struct nvc0_gr_init *init;
 
 	pack_for_each_init(init, pack, p) {
 		u32 next = init->addr + init->count * init->pitch;
@@ -669,10 +669,10 @@ nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
 }
 
 void
-nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
+nvc0_gr_icmd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
 {
-	const struct nvc0_graph_pack *pack;
-	const struct nvc0_graph_init *init;
+	const struct nvc0_gr_pack *pack;
+	const struct nvc0_gr_init *init;
 	u32 data = 0;
 
 	nv_wr32(priv, 0x400208, 0x80000000);
@@ -697,10 +697,10 @@ nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
 }
 
 void
-nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
+nvc0_gr_mthd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
 {
-	const struct nvc0_graph_pack *pack;
-	const struct nvc0_graph_init *init;
+	const struct nvc0_gr_pack *pack;
+	const struct nvc0_gr_init *init;
 	u32 data = 0;
 
 	pack_for_each_init(init, pack, p) {
@@ -721,9 +721,9 @@ nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
 }
 
 u64
-nvc0_graph_units(struct nouveau_graph *graph)
+nvc0_gr_units(struct nouveau_gr *gr)
 {
-	struct nvc0_graph_priv *priv = (void *)graph;
+	struct nvc0_gr_priv *priv = (void *)gr;
 	u64 cfg;
 
 	cfg  = (u32)priv->gpc_nr;
@@ -759,7 +759,7 @@ static const struct nouveau_enum nvc0_gpc_rop_error[] = {
 };
 
 static void
-nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc)
+nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc)
 {
 	u32 trap[4];
 	int i;
@@ -804,7 +804,7 @@ static const struct nouveau_bitfield nvc0_mp_global_error[] = {
 };
 
 static void
-nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc)
+nvc0_gr_trap_mp(struct nvc0_gr_priv *priv, int gpc, int tpc)
 {
 	u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
 	u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
@@ -822,7 +822,7 @@ nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc)
 }
 
 static void
-nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
+nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc)
 {
 	u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
 
@@ -834,7 +834,7 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
 	}
 
 	if (stat & 0x00000002) {
-		nvc0_graph_trap_mp(priv, gpc, tpc);
+		nvc0_gr_trap_mp(priv, gpc, tpc);
 		stat &= ~0x00000002;
 	}
 
@@ -858,13 +858,13 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
 }
 
 static void
-nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
+nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc)
 {
 	u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
 	int tpc;
 
 	if (stat & 0x00000001) {
-		nvc0_graph_trap_gpc_rop(priv, gpc);
+		nvc0_gr_trap_gpc_rop(priv, gpc);
 		stat &= ~0x00000001;
 	}
 
@@ -892,7 +892,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
 	for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
 		u32 mask = 0x00010000 << tpc;
 		if (stat & mask) {
-			nvc0_graph_trap_tpc(priv, gpc, tpc);
+			nvc0_gr_trap_tpc(priv, gpc, tpc);
 			nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
 			stat &= ~mask;
 		}
@@ -904,7 +904,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
 }
 
 static void
-nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
+nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
 {
 	u32 trap = nv_rd32(priv, 0x400108);
 	int rop, gpc, i;
@@ -980,7 +980,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
 		for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
 			u32 mask = 0x00000001 << gpc;
 			if (stat & mask) {
-				nvc0_graph_trap_gpc(priv, gpc);
+				nvc0_gr_trap_gpc(priv, gpc);
 				nv_wr32(priv, 0x400118, mask);
 				stat &= ~mask;
 			}
@@ -1009,7 +1009,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
 }
 
 static void
-nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
+nvc0_gr_ctxctl_debug_unit(struct nvc0_gr_priv *priv, u32 base)
 {
 	nv_error(priv, "%06x - done 0x%08x\n", base,
 		 nv_rd32(priv, base + 0x400));
@@ -1022,18 +1022,18 @@ nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
 }
 
 void
-nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
+nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *priv)
 {
 	u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
 	u32 gpc;
 
-	nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
+	nvc0_gr_ctxctl_debug_unit(priv, 0x409000);
 	for (gpc = 0; gpc < gpcnr; gpc++)
-		nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+		nvc0_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
 }
 
 static void
-nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
+nvc0_gr_ctxctl_isr(struct nvc0_gr_priv *priv)
 {
 	u32 stat = nv_rd32(priv, 0x409c18);
 
@@ -1059,26 +1059,26 @@ nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
 
 	if (stat & 0x00080000) {
 		nv_error(priv, "FECS watchdog timeout\n");
-		nvc0_graph_ctxctl_debug(priv);
+		nvc0_gr_ctxctl_debug(priv);
 		nv_wr32(priv, 0x409c20, 0x00080000);
 		stat &= ~0x00080000;
 	}
 
 	if (stat) {
 		nv_error(priv, "FECS 0x%08x\n", stat);
-		nvc0_graph_ctxctl_debug(priv);
+		nvc0_gr_ctxctl_debug(priv);
 		nv_wr32(priv, 0x409c20, stat);
 	}
 }
 
 static void
-nvc0_graph_intr(struct nouveau_subdev *subdev)
+nvc0_gr_intr(struct nouveau_subdev *subdev)
 {
 	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 	struct nouveau_engine *engine = nv_engine(subdev);
 	struct nouveau_object *engctx;
 	struct nouveau_handle *handle;
-	struct nvc0_graph_priv *priv = (void *)subdev;
+	struct nvc0_gr_priv *priv = (void *)subdev;
 	u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
 	u32 stat = nv_rd32(priv, 0x400100);
 	u32 addr = nv_rd32(priv, 0x400704);
@@ -1127,13 +1127,13 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
 	if (stat & 0x00200000) {
 		nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
 			 nouveau_client_name(engctx));
-		nvc0_graph_trap_intr(priv);
+		nvc0_gr_trap_intr(priv);
 		nv_wr32(priv, 0x400100, 0x00200000);
 		stat &= ~0x00200000;
 	}
 
 	if (stat & 0x00080000) {
-		nvc0_graph_ctxctl_isr(priv);
+		nvc0_gr_ctxctl_isr(priv);
 		nv_wr32(priv, 0x400100, 0x00080000);
 		stat &= ~0x00080000;
 	}
@@ -1148,8 +1148,8 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
 }
 
 void
-nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
-		   struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
+nvc0_gr_init_fw(struct nvc0_gr_priv *priv, u32 fuc_base,
+		   struct nvc0_gr_fuc *code, struct nvc0_gr_fuc *data)
 {
 	int i;
 
@@ -1170,12 +1170,12 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
 }
 
 static void
-nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
-		       const struct nvc0_graph_pack *pack,
+nvc0_gr_init_csdata(struct nvc0_gr_priv *priv,
+		       const struct nvc0_gr_pack *pack,
 		       u32 falcon, u32 starstar, u32 base)
 {
-	const struct nvc0_graph_pack *iter;
-	const struct nvc0_graph_init *init;
+	const struct nvc0_gr_pack *iter;
+	const struct nvc0_gr_init *init;
 	u32 addr = ~0, prev = ~0, xfer = 0;
 	u32 star, temp;
 
@@ -1211,18 +1211,18 @@ nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
 }
 
 int
-nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
+nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
 {
-	struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
+	struct nvc0_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
 	struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
 	if (priv->firmware) {
 		/* load fuc microcode */
 		nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
-		nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c,
+		nvc0_gr_init_fw(priv, 0x409000, &priv->fuc409c,
 						   &priv->fuc409d);
-		nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac,
+		nvc0_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
 						   &priv->fuc41ad);
 		nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
@@ -1337,17 +1337,17 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
 	/* load register lists */
-	nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
-	nvc0_graph_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
-	nvc0_graph_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
-	nvc0_graph_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
+	nvc0_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
+	nvc0_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
+	nvc0_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
+	nvc0_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
 
 	/* start HUB ucode running, it'll init the GPCs */
 	nv_wr32(priv, 0x40910c, 0x00000000);
 	nv_wr32(priv, 0x409100, 0x00000002);
 	if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
 		nv_error(priv, "HUB_INIT timed out\n");
-		nvc0_graph_ctxctl_debug(priv);
+		nvc0_gr_ctxctl_debug(priv);
 		return -EBUSY;
 	}
 
@@ -1364,17 +1364,17 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
 }
 
 int
-nvc0_graph_init(struct nouveau_object *object)
+nvc0_gr_init(struct nouveau_object *object)
 {
-	struct nvc0_graph_oclass *oclass = (void *)object->oclass;
-	struct nvc0_graph_priv *priv = (void *)object;
+	struct nvc0_gr_oclass *oclass = (void *)object->oclass;
+	struct nvc0_gr_priv *priv = (void *)object;
 	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
 	u32 data[TPC_MAX / 8] = {};
 	u8  tpcnr[GPC_MAX];
 	int gpc, tpc, rop;
 	int ret, i;
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -1387,7 +1387,7 @@ nvc0_graph_init(struct nouveau_object *object)
 	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
 	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 
-	nvc0_graph_mmio(priv, oclass->mmio);
+	nvc0_gr_mmio(priv, oclass->mmio);
 
 	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
 	for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
@@ -1470,21 +1470,21 @@ nvc0_graph_init(struct nouveau_object *object)
 
 	nv_wr32(priv, 0x400054, 0x34ce3464);
 
-	nvc0_graph_zbc_init(priv);
+	nvc0_gr_zbc_init(priv);
 
-	return nvc0_graph_init_ctxctl(priv);
+	return nvc0_gr_init_ctxctl(priv);
 }
 
 static void
-nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
+nvc0_gr_dtor_fw(struct nvc0_gr_fuc *fuc)
 {
 	kfree(fuc->data);
 	fuc->data = NULL;
 }
 
 int
-nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
-		   struct nvc0_graph_fuc *fuc)
+nvc0_gr_ctor_fw(struct nvc0_gr_priv *priv, const char *fwname,
+		   struct nvc0_gr_fuc *fuc)
 {
 	struct nouveau_device *device = nv_device(priv);
 	const struct firmware *fw;
@@ -1509,31 +1509,31 @@ nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
 }
 
 void
-nvc0_graph_dtor(struct nouveau_object *object)
+nvc0_gr_dtor(struct nouveau_object *object)
 {
-	struct nvc0_graph_priv *priv = (void *)object;
+	struct nvc0_gr_priv *priv = (void *)object;
 
 	kfree(priv->data);
 
-	nvc0_graph_dtor_fw(&priv->fuc409c);
-	nvc0_graph_dtor_fw(&priv->fuc409d);
-	nvc0_graph_dtor_fw(&priv->fuc41ac);
-	nvc0_graph_dtor_fw(&priv->fuc41ad);
+	nvc0_gr_dtor_fw(&priv->fuc409c);
+	nvc0_gr_dtor_fw(&priv->fuc409d);
+	nvc0_gr_dtor_fw(&priv->fuc41ac);
+	nvc0_gr_dtor_fw(&priv->fuc41ad);
 
 	nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 	nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 
-	nouveau_graph_destroy(&priv->base);
+	nouveau_gr_destroy(&priv->base);
 }
 
 int
-nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		struct nouveau_oclass *bclass, void *data, u32 size,
 		struct nouveau_object **pobject)
 {
-	struct nvc0_graph_oclass *oclass = (void *)bclass;
+	struct nvc0_gr_oclass *oclass = (void *)bclass;
 	struct nouveau_device *device = nv_device(parent);
-	struct nvc0_graph_priv *priv;
+	struct nvc0_gr_priv *priv;
 	bool use_ext_fw, enable;
 	int ret, i, j;
 
@@ -1541,22 +1541,22 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 				     oclass->fecs.ucode == NULL);
 	enable = use_ext_fw || oclass->fecs.ucode != NULL;
 
-	ret = nouveau_graph_create(parent, engine, bclass, enable, &priv);
+	ret = nouveau_gr_create(parent, engine, bclass, enable, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x08001000;
-	nv_subdev(priv)->intr = nvc0_graph_intr;
+	nv_subdev(priv)->intr = nvc0_gr_intr;
 
-	priv->base.units = nvc0_graph_units;
+	priv->base.units = nvc0_gr_units;
 
 	if (use_ext_fw) {
 		nv_info(priv, "using external firmware\n");
-		if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
-		    nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
-		    nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
-		    nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
+		if (nvc0_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
+		    nvc0_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
+		    nvc0_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
+		    nvc0_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
 			return -ENODEV;
 		priv->firmware = true;
 	}
@@ -1632,8 +1632,8 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 
 #include "fuc/hubnvc0.fuc3.h"
 
-struct nvc0_graph_ucode
-nvc0_graph_fecs_ucode = {
+struct nvc0_gr_ucode
+nvc0_gr_fecs_ucode = {
 	.code.data = nvc0_grhub_code,
 	.code.size = sizeof(nvc0_grhub_code),
 	.data.data = nvc0_grhub_data,
@@ -1642,8 +1642,8 @@ nvc0_graph_fecs_ucode = {
 
 #include "fuc/gpcnvc0.fuc3.h"
 
-struct nvc0_graph_ucode
-nvc0_graph_gpccs_ucode = {
+struct nvc0_gr_ucode
+nvc0_gr_gpccs_ucode = {
 	.code.data = nvc0_grgpc_code,
 	.code.size = sizeof(nvc0_grgpc_code),
 	.data.data = nvc0_grgpc_data,
@@ -1651,17 +1651,17 @@ nvc0_graph_gpccs_ucode = {
 };
 
 struct nouveau_oclass *
-nvc0_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc0_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xc0),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nvc0_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nvc0_grctx_oclass,
-	.sclass =  nvc0_graph_sclass,
-	.mmio = nvc0_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
+	.sclass =  nvc0_gr_sclass,
+	.mmio = nvc0_gr_pack_mmio,
+	.fecs.ucode = &nvc0_gr_fecs_ucode,
+	.gpccs.ucode = &nvc0_gr_gpccs_ucode,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h

@@ -0,0 +1,270 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#ifndef __NVC0_GR_H__
+#define __NVC0_GR_H__
+
+#include <core/client.h>
+#include <core/handle.h>
+#include <core/gpuobj.h>
+#include <core/option.h>
+
+#include <nvif/unpack.h>
+#include <nvif/class.h>
+
+#include <subdev/fb.h>
+#include <subdev/mmu.h>
+#include <subdev/bar.h>
+#include <subdev/timer.h>
+#include <subdev/mc.h>
+#include <subdev/ltc.h>
+
+#include <engine/fifo.h>
+#include <engine/gr.h>
+
+#include "fuc/os.h"
+
+#define GPC_MAX 32
+#define TPC_MAX (GPC_MAX * 8)
+
+#define ROP_BCAST(r)      (0x408800 + (r))
+#define ROP_UNIT(u, r)    (0x410000 + (u) * 0x400 + (r))
+#define GPC_BCAST(r)      (0x418000 + (r))
+#define GPC_UNIT(t, r)    (0x500000 + (t) * 0x8000 + (r))
+#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
+#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
+
+struct nvc0_gr_data {
+	u32 size;
+	u32 align;
+	u32 access;
+};
+
+struct nvc0_gr_mmio {
+	u32 addr;
+	u32 data;
+	u32 shift;
+	int buffer;
+};
+
+struct nvc0_gr_fuc {
+	u32 *data;
+	u32  size;
+};
+
+struct nvc0_gr_zbc_color {
+	u32 format;
+	u32 ds[4];
+	u32 l2[4];
+};
+
+struct nvc0_gr_zbc_depth {
+	u32 format;
+	u32 ds;
+	u32 l2;
+};
+
+struct nvc0_gr_priv {
+	struct nouveau_gr base;
+
+	struct nvc0_gr_fuc fuc409c;
+	struct nvc0_gr_fuc fuc409d;
+	struct nvc0_gr_fuc fuc41ac;
+	struct nvc0_gr_fuc fuc41ad;
+	bool firmware;
+
+	struct nvc0_gr_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT];
+	struct nvc0_gr_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
+
+	u8 rop_nr;
+	u8 gpc_nr;
+	u8 tpc_nr[GPC_MAX];
+	u8 tpc_total;
+	u8 ppc_nr[GPC_MAX];
+	u8 ppc_tpc_nr[GPC_MAX][4];
+
+	struct nouveau_gpuobj *unk4188b4;
+	struct nouveau_gpuobj *unk4188b8;
+
+	struct nvc0_gr_data mmio_data[4];
+	struct nvc0_gr_mmio mmio_list[4096/8];
+	u32  size;
+	u32 *data;
+
+	u8 magic_not_rop_nr;
+};
+
+struct nvc0_gr_chan {
+	struct nouveau_gr_chan base;
+
+	struct nouveau_gpuobj *mmio;
+	struct nouveau_vma mmio_vma;
+	int mmio_nr;
+	struct {
+		struct nouveau_gpuobj *mem;
+		struct nouveau_vma vma;
+	} data[4];
+};
+
+int  nvc0_gr_context_ctor(struct nouveau_object *, struct nouveau_object *,
+			     struct nouveau_oclass *, void *, u32,
+			     struct nouveau_object **);
+void nvc0_gr_context_dtor(struct nouveau_object *);
+
+void nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *);
+
+u64  nvc0_gr_units(struct nouveau_gr *);
+int  nvc0_gr_ctor(struct nouveau_object *, struct nouveau_object *,
+		     struct nouveau_oclass *, void *data, u32 size,
+		     struct nouveau_object **);
+void nvc0_gr_dtor(struct nouveau_object *);
+int  nvc0_gr_init(struct nouveau_object *);
+void nvc0_gr_zbc_init(struct nvc0_gr_priv *);
+
+int  nve4_gr_fini(struct nouveau_object *, bool);
+int  nve4_gr_init(struct nouveau_object *);
+
+int  nvf0_gr_fini(struct nouveau_object *, bool);
+
+extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
+
+extern struct nouveau_oclass nvc0_gr_sclass[];
+extern struct nouveau_omthds nvc0_gr_9097_omthds[];
+extern struct nouveau_omthds nvc0_gr_90c0_omthds[];
+extern struct nouveau_oclass nvc8_gr_sclass[];
+extern struct nouveau_oclass nvf0_gr_sclass[];
+
+struct nvc0_gr_init {
+	u32 addr;
+	u8  count;
+	u8  pitch;
+	u32 data;
+};
+
+struct nvc0_gr_pack {
+	const struct nvc0_gr_init *init;
+	u32 type;
+};
+
+#define pack_for_each_init(init, pack, head)                                   \
+	for (pack = head; pack && pack->init; pack++)                          \
+		  for (init = pack->init; init && init->count; init++)
+
+struct nvc0_gr_ucode {
+	struct nvc0_gr_fuc code;
+	struct nvc0_gr_fuc data;
+};
+
+extern struct nvc0_gr_ucode nvc0_gr_fecs_ucode;
+extern struct nvc0_gr_ucode nvc0_gr_gpccs_ucode;
+
+extern struct nvc0_gr_ucode nvf0_gr_fecs_ucode;
+extern struct nvc0_gr_ucode nvf0_gr_gpccs_ucode;
+
+struct nvc0_gr_oclass {
+	struct nouveau_oclass base;
+	struct nouveau_oclass **cclass;
+	struct nouveau_oclass *sclass;
+	const struct nvc0_gr_pack *mmio;
+	struct {
+		struct nvc0_gr_ucode *ucode;
+	} fecs;
+	struct {
+		struct nvc0_gr_ucode *ucode;
+	} gpccs;
+	int ppc_nr;
+};
+
+void nvc0_gr_mmio(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
+void nvc0_gr_icmd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
+void nvc0_gr_mthd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
+int  nvc0_gr_init_ctxctl(struct nvc0_gr_priv *);
+
+/* register init value lists */
+
+extern const struct nvc0_gr_init nvc0_gr_init_main_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_fe_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_pri_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_rstr2d_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_pd_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_scc_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_prop_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_setup_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_crstr_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_setup_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_zcull_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_gpm_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_gcc_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_tpccs_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_pe_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_l1c_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_tpccs_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_mpc_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_be_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_fe_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_pe_1[];
+
+extern const struct nvc0_gr_init nvc4_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvc4_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvc4_gr_init_sm_0[];
+
+extern const struct nvc0_gr_init nvc1_gr_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc1_gr_init_setup_1[];
+
+extern const struct nvc0_gr_init nvd9_gr_init_pd_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_prop_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_gpm_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvd9_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_sm_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_fe_1[];
+
+extern const struct nvc0_gr_init nvd7_gr_init_pes_0[];
+extern const struct nvc0_gr_init nvd7_gr_init_wwdx_0[];
+extern const struct nvc0_gr_init nvd7_gr_init_cbm_0[];
+
+extern const struct nvc0_gr_init nve4_gr_init_main_0[];
+extern const struct nvc0_gr_init nve4_gr_init_tpccs_0[];
+extern const struct nvc0_gr_init nve4_gr_init_pe_0[];
+extern const struct nvc0_gr_init nve4_gr_init_be_0[];
+extern const struct nvc0_gr_pack nve4_gr_pack_mmio[];
+
+extern const struct nvc0_gr_init nvf0_gr_init_fe_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_sked_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_cwd_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvf0_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_sm_0[];
+
+extern const struct nvc0_gr_init nv108_gr_init_gpc_unk_0[];
+
+
+#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c

@@ -30,12 +30,12 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nvc1_graph_sclass[] = {
+nvc1_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0x9039, &nouveau_object_ofuncs },
-	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
@@ -43,8 +43,8 @@ nvc1_graph_sclass[] = {
  * PGRAPH register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
-nvc1_graph_init_gpc_unk_0[] = {
+const struct nvc0_gr_init
+nvc1_gr_init_gpc_unk_0[] = {
 	{ 0x418604,   1, 0x04, 0x00000000 },
 	{ 0x418680,   1, 0x04, 0x00000000 },
 	{ 0x418714,   1, 0x04, 0x00000000 },
@@ -52,16 +52,16 @@ nvc1_graph_init_gpc_unk_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc1_graph_init_setup_1[] = {
+const struct nvc0_gr_init
+nvc1_gr_init_setup_1[] = {
 	{ 0x4188c8,   2, 0x04, 0x00000000 },
 	{ 0x4188d0,   1, 0x04, 0x00010000 },
 	{ 0x4188d4,   1, 0x04, 0x00000001 },
 	{}
 };
 
-static const struct nvc0_graph_init
-nvc1_graph_init_gpc_unk_1[] = {
+static const struct nvc0_gr_init
+nvc1_gr_init_gpc_unk_1[] = {
 	{ 0x418d00,   1, 0x04, 0x00000000 },
 	{ 0x418f08,   1, 0x04, 0x00000000 },
 	{ 0x418e00,   1, 0x04, 0x00000003 },
@@ -69,8 +69,8 @@ nvc1_graph_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nvc1_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvc1_gr_init_pe_0[] = {
 	{ 0x41980c,   1, 0x04, 0x00000010 },
 	{ 0x419810,   1, 0x04, 0x00000000 },
 	{ 0x419814,   1, 0x04, 0x00000004 },
@@ -81,34 +81,34 @@ nvc1_graph_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvc1_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc4_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc1_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc4_graph_init_tex_0 },
-	{ nvc1_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc4_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvc1_gr_pack_mmio[] = {
+	{ nvc0_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvc0_gr_init_pd_0 },
+	{ nvc4_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvc0_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvc0_gr_init_gpm_0 },
+	{ nvc1_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nvc0_gr_init_tpccs_0 },
+	{ nvc4_gr_init_tex_0 },
+	{ nvc1_gr_init_pe_0 },
+	{ nvc0_gr_init_l1c_0 },
+	{ nvc0_gr_init_wwdx_0 },
+	{ nvc0_gr_init_tpccs_1 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvc4_gr_init_sm_0 },
+	{ nvc0_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -117,17 +117,17 @@ nvc1_graph_pack_mmio[] = {
  ******************************************************************************/
 
 struct nouveau_oclass *
-nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc1_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xc1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nvc0_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nvc1_grctx_oclass,
-	.sclass = nvc1_graph_sclass,
-	.mmio = nvc1_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
+	.sclass = nvc1_gr_sclass,
+	.mmio = nvc1_gr_pack_mmio,
+	.fecs.ucode = &nvc0_gr_fecs_ucode,
+	.gpccs.ucode = &nvc0_gr_gpccs_ucode,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c

@@ -29,8 +29,8 @@
  * PGRAPH register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
-nvc4_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvc4_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405900,   1, 0x04, 0x00002834 },
@@ -38,8 +38,8 @@ nvc4_graph_init_ds_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc4_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvc4_gr_init_tex_0[] = {
 	{ 0x419ab0,   1, 0x04, 0x00000000 },
 	{ 0x419ac8,   1, 0x04, 0x00000000 },
 	{ 0x419ab8,   1, 0x04, 0x000000e7 },
@@ -47,8 +47,8 @@ nvc4_graph_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nvc4_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvc4_gr_init_pe_0[] = {
 	{ 0x41980c,   3, 0x04, 0x00000000 },
 	{ 0x419844,   1, 0x04, 0x00000000 },
 	{ 0x41984c,   1, 0x04, 0x00005bc5 },
@@ -57,8 +57,8 @@ nvc4_graph_init_pe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvc4_graph_init_sm_0[] = {
+const struct nvc0_gr_init
+nvc4_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000000 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ea4,   1, 0x04, 0x00000100 },
@@ -76,34 +76,34 @@ nvc4_graph_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvc4_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc4_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc0_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc0_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc4_graph_init_tex_0 },
-	{ nvc4_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc4_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvc4_gr_pack_mmio[] = {
+	{ nvc0_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvc0_gr_init_pd_0 },
+	{ nvc4_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvc0_gr_init_prop_0 },
+	{ nvc0_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc0_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvc0_gr_init_gpm_0 },
+	{ nvc0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nvc0_gr_init_tpccs_0 },
+	{ nvc4_gr_init_tex_0 },
+	{ nvc4_gr_init_pe_0 },
+	{ nvc0_gr_init_l1c_0 },
+	{ nvc0_gr_init_wwdx_0 },
+	{ nvc0_gr_init_tpccs_1 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvc4_gr_init_sm_0 },
+	{ nvc0_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -112,17 +112,17 @@ nvc4_graph_pack_mmio[] = {
  ******************************************************************************/
 
 struct nouveau_oclass *
-nvc4_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc4_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xc3),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nvc0_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nvc4_grctx_oclass,
-	.sclass = nvc0_graph_sclass,
-	.mmio = nvc4_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
+	.sclass = nvc0_gr_sclass,
+	.mmio = nvc4_gr_pack_mmio,
+	.fecs.ucode = &nvc0_gr_fecs_ucode,
+	.gpccs.ucode = &nvc0_gr_gpccs_ucode,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c

@@ -30,13 +30,13 @@
  ******************************************************************************/
 
 struct nouveau_oclass
-nvc8_graph_sclass[] = {
+nvc8_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0x9039, &nouveau_object_ofuncs },
-	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ FERMI_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
@@ -44,8 +44,8 @@ nvc8_graph_sclass[] = {
  * PGRAPH register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
-nvc8_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+nvc8_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000000 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ea4,   1, 0x04, 0x00000100 },
@@ -62,35 +62,35 @@ nvc8_graph_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvc8_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvc0_graph_init_pd_0 },
-	{ nvc0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvc0_graph_init_prop_0 },
-	{ nvc0_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvc0_graph_init_gpm_0 },
-	{ nvc0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvc0_graph_init_tex_0 },
-	{ nvc0_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_wwdx_0 },
-	{ nvc0_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvc8_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
-	{ nvc0_graph_init_pe_1 },
+static const struct nvc0_gr_pack
+nvc8_gr_pack_mmio[] = {
+	{ nvc0_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvc0_gr_init_pd_0 },
+	{ nvc0_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvc0_gr_init_prop_0 },
+	{ nvc0_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvc0_gr_init_gpm_0 },
+	{ nvc0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nvc0_gr_init_tpccs_0 },
+	{ nvc0_gr_init_tex_0 },
+	{ nvc0_gr_init_pe_0 },
+	{ nvc0_gr_init_l1c_0 },
+	{ nvc0_gr_init_wwdx_0 },
+	{ nvc0_gr_init_tpccs_1 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvc8_gr_init_sm_0 },
+	{ nvc0_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
+	{ nvc0_gr_init_pe_1 },
 	{}
 };
 
@@ -99,17 +99,17 @@ nvc8_graph_pack_mmio[] = {
  ******************************************************************************/
 
 struct nouveau_oclass *
-nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc8_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xc8),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nvc0_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nvc8_grctx_oclass,
-	.sclass = nvc8_graph_sclass,
-	.mmio = nvc8_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
+	.sclass = nvc8_gr_sclass,
+	.mmio = nvc8_gr_pack_mmio,
+	.fecs.ucode = &nvc0_gr_fecs_ucode,
+	.gpccs.ucode = &nvc0_gr_gpccs_ucode,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c

@@ -29,8 +29,8 @@
  * PGRAPH register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
-nvd7_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvd7_gr_init_pe_0[] = {
 	{ 0x41980c,   1, 0x04, 0x00000010 },
 	{ 0x419844,   1, 0x04, 0x00000000 },
 	{ 0x41984c,   1, 0x04, 0x00005bc8 },
@@ -38,8 +38,8 @@ nvd7_graph_init_pe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvd7_graph_init_pes_0[] = {
+const struct nvc0_gr_init
+nvd7_gr_init_pes_0[] = {
 	{ 0x41be04,   1, 0x04, 0x00000000 },
 	{ 0x41be08,   1, 0x04, 0x00000004 },
 	{ 0x41be0c,   1, 0x04, 0x00000000 },
@@ -48,50 +48,50 @@ nvd7_graph_init_pes_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvd7_graph_init_wwdx_0[] = {
+const struct nvc0_gr_init
+nvd7_gr_init_wwdx_0[] = {
 	{ 0x41bfd4,   1, 0x04, 0x00800000 },
 	{ 0x41bfdc,   1, 0x04, 0x00000000 },
 	{ 0x41bff8,   2, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvd7_graph_init_cbm_0[] = {
+const struct nvc0_gr_init
+nvd7_gr_init_cbm_0[] = {
 	{ 0x41becc,   1, 0x04, 0x00000000 },
 	{ 0x41bee8,   2, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvd7_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvd9_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvd9_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvd9_graph_init_tex_0 },
-	{ nvd7_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvd9_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvd9_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvd7_gr_pack_mmio[] = {
+	{ nvc0_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nvd9_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nvd9_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nvc0_gr_init_tpccs_0 },
+	{ nvd9_gr_init_tex_0 },
+	{ nvd7_gr_init_pe_0 },
+	{ nvc0_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvd9_gr_init_sm_0 },
+	{ nvd7_gr_init_pes_0 },
+	{ nvd7_gr_init_wwdx_0 },
+	{ nvd7_gr_init_cbm_0 },
+	{ nvc0_gr_init_be_0 },
+	{ nvd9_gr_init_fe_1 },
 	{}
 };
 
@@ -101,8 +101,8 @@ nvd7_graph_pack_mmio[] = {
 
 #include "fuc/hubnvd7.fuc3.h"
 
-struct nvc0_graph_ucode
-nvd7_graph_fecs_ucode = {
+struct nvc0_gr_ucode
+nvd7_gr_fecs_ucode = {
 	.code.data = nvd7_grhub_code,
 	.code.size = sizeof(nvd7_grhub_code),
 	.data.data = nvd7_grhub_data,
@@ -111,8 +111,8 @@ nvd7_graph_fecs_ucode = {
 
 #include "fuc/gpcnvd7.fuc3.h"
 
-struct nvc0_graph_ucode
-nvd7_graph_gpccs_ucode = {
+struct nvc0_gr_ucode
+nvd7_gr_gpccs_ucode = {
 	.code.data = nvd7_grgpc_code,
 	.code.size = sizeof(nvd7_grgpc_code),
 	.data.data = nvd7_grgpc_data,
@@ -120,18 +120,18 @@ nvd7_graph_gpccs_ucode = {
 };
 
 struct nouveau_oclass *
-nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
+nvd7_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xd7),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nvc0_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nvd7_grctx_oclass,
-	.sclass = nvc8_graph_sclass,
-	.mmio = nvd7_graph_pack_mmio,
-	.fecs.ucode = &nvd7_graph_fecs_ucode,
-	.gpccs.ucode = &nvd7_graph_gpccs_ucode,
+	.sclass = nvc8_gr_sclass,
+	.mmio = nvd7_gr_pack_mmio,
+	.fecs.ucode = &nvd7_gr_fecs_ucode,
+	.gpccs.ucode = &nvd7_gr_gpccs_ucode,
 	.ppc_nr = 1,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c

@@ -29,15 +29,15 @@
  * PGRAPH register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
-nvd9_graph_init_pd_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_pd_0[] = {
 	{ 0x406024,   1, 0x04, 0x00000000 },
 	{ 0x4064f0,   3, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405900,   1, 0x04, 0x00002834 },
@@ -46,15 +46,15 @@ nvd9_graph_init_ds_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_prop_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_prop_0[] = {
 	{ 0x418408,   1, 0x04, 0x00000000 },
 	{ 0x4184a0,   3, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_gpm_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_gpm_0[] = {
 	{ 0x418c04,   1, 0x04, 0x00000000 },
 	{ 0x418c64,   2, 0x04, 0x00000000 },
 	{ 0x418c88,   1, 0x04, 0x00000000 },
@@ -62,8 +62,8 @@ nvd9_graph_init_gpm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_gpc_unk_1[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_gpc_unk_1[] = {
 	{ 0x418d00,   1, 0x04, 0x00000000 },
 	{ 0x418d28,   2, 0x04, 0x00000000 },
 	{ 0x418f00,   1, 0x04, 0x00000000 },
@@ -75,8 +75,8 @@ nvd9_graph_init_gpc_unk_1[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_tex_0[] = {
 	{ 0x419ab0,   1, 0x04, 0x00000000 },
 	{ 0x419ac8,   1, 0x04, 0x00000000 },
 	{ 0x419ab8,   1, 0x04, 0x000000e7 },
@@ -85,8 +85,8 @@ nvd9_graph_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nvd9_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvd9_gr_init_pe_0[] = {
 	{ 0x41980c,   1, 0x04, 0x00000010 },
 	{ 0x419810,   1, 0x04, 0x00000000 },
 	{ 0x419814,   1, 0x04, 0x00000004 },
@@ -97,23 +97,23 @@ nvd9_graph_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nvd9_graph_init_wwdx_0[] = {
+static const struct nvc0_gr_init
+nvd9_gr_init_wwdx_0[] = {
 	{ 0x419bd4,   1, 0x04, 0x00800000 },
 	{ 0x419bdc,   1, 0x04, 0x00000000 },
 	{ 0x419bf8,   2, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-nvd9_graph_init_tpccs_1[] = {
+static const struct nvc0_gr_init
+nvd9_gr_init_tpccs_1[] = {
 	{ 0x419d2c,   1, 0x04, 0x00000000 },
 	{ 0x419d48,   2, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_sm_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000000 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ea4,   1, 0x04, 0x00000100 },
@@ -131,42 +131,42 @@ nvd9_graph_init_sm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvd9_graph_init_fe_1[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_fe_1[] = {
 	{ 0x40402c,   1, 0x04, 0x00000000 },
 	{ 0x4040f0,   1, 0x04, 0x00000000 },
 	{ 0x404174,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvd9_graph_pack_mmio[] = {
-	{ nvc0_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvd9_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvd9_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nvc0_graph_init_tpccs_0 },
-	{ nvd9_graph_init_tex_0 },
-	{ nvd9_graph_init_pe_0 },
-	{ nvc0_graph_init_l1c_0 },
-	{ nvd9_graph_init_wwdx_0 },
-	{ nvd9_graph_init_tpccs_1 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvd9_graph_init_sm_0 },
-	{ nvc0_graph_init_be_0 },
-	{ nvd9_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvd9_gr_pack_mmio[] = {
+	{ nvc0_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nvd9_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nvd9_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nvc0_gr_init_tpccs_0 },
+	{ nvd9_gr_init_tex_0 },
+	{ nvd9_gr_init_pe_0 },
+	{ nvc0_gr_init_l1c_0 },
+	{ nvd9_gr_init_wwdx_0 },
+	{ nvd9_gr_init_tpccs_1 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvd9_gr_init_sm_0 },
+	{ nvc0_gr_init_be_0 },
+	{ nvd9_gr_init_fe_1 },
 	{}
 };
 
@@ -175,17 +175,17 @@ nvd9_graph_pack_mmio[] = {
  ******************************************************************************/
 
 struct nouveau_oclass *
-nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
+nvd9_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xd9),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nvc0_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nvc0_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nvd9_grctx_oclass,
-	.sclass = nvc8_graph_sclass,
-	.mmio = nvd9_graph_pack_mmio,
-	.fecs.ucode = &nvc0_graph_fecs_ucode,
-	.gpccs.ucode = &nvc0_graph_gpccs_ucode,
+	.sclass = nvc8_gr_sclass,
+	.mmio = nvd9_gr_pack_mmio,
+	.fecs.ucode = &nvc0_gr_fecs_ucode,
+	.gpccs.ucode = &nvc0_gr_gpccs_ucode,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c

@@ -32,11 +32,11 @@
  ******************************************************************************/
 
 static struct nouveau_oclass
-nve4_graph_sclass[] = {
+nve4_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0xa040, &nouveau_object_ofuncs },
-	{ KEPLER_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ KEPLER_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
@@ -44,8 +44,8 @@ nve4_graph_sclass[] = {
  * PGRAPH register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
-nve4_graph_init_main_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_main_0[] = {
 	{ 0x400080,   1, 0x04, 0x003083c2 },
 	{ 0x400088,   1, 0x04, 0x0001ffe7 },
 	{ 0x40008c,   1, 0x04, 0x00000000 },
@@ -60,8 +60,8 @@ nve4_graph_init_main_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_graph_init_ds_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405900,   1, 0x04, 0x0000ff34 },
@@ -70,20 +70,20 @@ nve4_graph_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_graph_init_sked_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_sked_0[] = {
 	{ 0x407010,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_graph_init_cwd_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_cwd_0[] = {
 	{ 0x405b50,   1, 0x04, 0x00000000 },
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_graph_init_gpc_unk_1[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_gpc_unk_1[] = {
 	{ 0x418d00,   1, 0x04, 0x00000000 },
 	{ 0x418d28,   2, 0x04, 0x00000000 },
 	{ 0x418f00,   1, 0x04, 0x00000000 },
@@ -95,15 +95,15 @@ nve4_graph_init_gpc_unk_1[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nve4_graph_init_tpccs_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_tpccs_0[] = {
 	{ 0x419d0c,   1, 0x04, 0x00000000 },
 	{ 0x419d10,   1, 0x04, 0x00000014 },
 	{}
 };
 
-const struct nvc0_graph_init
-nve4_graph_init_pe_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_pe_0[] = {
 	{ 0x41980c,   1, 0x04, 0x00000010 },
 	{ 0x419844,   1, 0x04, 0x00000000 },
 	{ 0x419850,   1, 0x04, 0x00000004 },
@@ -111,8 +111,8 @@ nve4_graph_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419ca8,   1, 0x04, 0x00000000 },
 	{ 0x419cb0,   1, 0x04, 0x01000000 },
@@ -125,8 +125,8 @@ nve4_graph_init_l1c_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000000 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ee4,   1, 0x04, 0x00000000 },
@@ -139,8 +139,8 @@ nve4_graph_init_sm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nve4_graph_init_be_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_be_0[] = {
 	{ 0x40880c,   1, 0x04, 0x00000000 },
 	{ 0x408850,   1, 0x04, 0x00000004 },
 	{ 0x408910,   9, 0x04, 0x00000000 },
@@ -153,37 +153,37 @@ nve4_graph_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
-nve4_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvc0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nve4_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nve4_graph_init_sked_0 },
-	{ nve4_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nve4_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvd9_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ nve4_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nve4_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+const struct nvc0_gr_pack
+nve4_gr_pack_mmio[] = {
+	{ nve4_gr_init_main_0 },
+	{ nvc0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nve4_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nve4_gr_init_sked_0 },
+	{ nve4_gr_init_cwd_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nve4_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nve4_gr_init_tpccs_0 },
+	{ nvd9_gr_init_tex_0 },
+	{ nve4_gr_init_pe_0 },
+	{ nve4_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nve4_gr_init_sm_0 },
+	{ nvd7_gr_init_pes_0 },
+	{ nvd7_gr_init_wwdx_0 },
+	{ nvd7_gr_init_cbm_0 },
+	{ nve4_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -192,10 +192,10 @@ nve4_graph_pack_mmio[] = {
  ******************************************************************************/
 
 int
-nve4_graph_init(struct nouveau_object *object)
+nve4_gr_init(struct nouveau_object *object)
 {
-	struct nvc0_graph_oclass *oclass = (void *)object->oclass;
-	struct nvc0_graph_priv *priv = (void *)object;
+	struct nvc0_gr_oclass *oclass = (void *)object->oclass;
+	struct nvc0_gr_priv *priv = (void *)object;
 	struct nouveau_pmu *pmu = nouveau_pmu(priv);
 	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
 	u32 data[TPC_MAX / 8] = {};
@@ -206,7 +206,7 @@ nve4_graph_init(struct nouveau_object *object)
 	if (pmu)
 		pmu->pgob(pmu, false);
 
-	ret = nouveau_graph_init(&priv->base);
+	ret = nouveau_gr_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -219,7 +219,7 @@ nve4_graph_init(struct nouveau_object *object)
 	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
 	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 
-	nvc0_graph_mmio(priv, oclass->mmio);
+	nvc0_gr_mmio(priv, oclass->mmio);
 
 	nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
 
@@ -304,15 +304,15 @@ nve4_graph_init(struct nouveau_object *object)
 
 	nv_wr32(priv, 0x400054, 0x34ce3464);
 
-	nvc0_graph_zbc_init(priv);
+	nvc0_gr_zbc_init(priv);
 
-	return nvc0_graph_init_ctxctl(priv);
+	return nvc0_gr_init_ctxctl(priv);
 }
 
 #include "fuc/hubnve0.fuc3.h"
 
-static struct nvc0_graph_ucode
-nve4_graph_fecs_ucode = {
+static struct nvc0_gr_ucode
+nve4_gr_fecs_ucode = {
 	.code.data = nve0_grhub_code,
 	.code.size = sizeof(nve0_grhub_code),
 	.data.data = nve0_grhub_data,
@@ -321,8 +321,8 @@ nve4_graph_fecs_ucode = {
 
 #include "fuc/gpcnve0.fuc3.h"
 
-static struct nvc0_graph_ucode
-nve4_graph_gpccs_ucode = {
+static struct nvc0_gr_ucode
+nve4_gr_gpccs_ucode = {
 	.code.data = nve0_grgpc_code,
 	.code.size = sizeof(nve0_grgpc_code),
 	.data.data = nve0_grgpc_data,
@@ -330,18 +330,18 @@ nve4_graph_gpccs_ucode = {
 };
 
 struct nouveau_oclass *
-nve4_graph_oclass = &(struct nvc0_graph_oclass) {
+nve4_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xe4),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &nve4_grctx_oclass,
-	.sclass = nve4_graph_sclass,
-	.mmio = nve4_graph_pack_mmio,
-	.fecs.ucode = &nve4_graph_fecs_ucode,
-	.gpccs.ucode = &nve4_graph_gpccs_ucode,
+	.sclass = nve4_gr_sclass,
+	.mmio = nve4_gr_pack_mmio,
+	.fecs.ucode = &nve4_gr_fecs_ucode,
+	.gpccs.ucode = &nve4_gr_gpccs_ucode,
 	.ppc_nr = 1,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c

@@ -30,11 +30,11 @@
  ******************************************************************************/
 
 struct nouveau_oclass
-nvf0_graph_sclass[] = {
+nvf0_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0xa140, &nouveau_object_ofuncs },
-	{ KEPLER_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ KEPLER_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
@@ -42,16 +42,16 @@ nvf0_graph_sclass[] = {
  * PGRAPH register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
-nvf0_graph_init_fe_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_fe_0[] = {
 	{ 0x40415c,   1, 0x04, 0x00000000 },
 	{ 0x404170,   1, 0x04, 0x00000000 },
 	{ 0x4041b4,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvf0_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_ds_0[] = {
 	{ 0x405844,   1, 0x04, 0x00ffffff },
 	{ 0x405850,   1, 0x04, 0x00000000 },
 	{ 0x405900,   1, 0x04, 0x0000ff00 },
@@ -60,23 +60,23 @@ nvf0_graph_init_ds_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvf0_graph_init_sked_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_sked_0[] = {
 	{ 0x407010,   1, 0x04, 0x00000000 },
 	{ 0x407040,   1, 0x04, 0x80440424 },
 	{ 0x407048,   1, 0x04, 0x0000000a },
 	{}
 };
 
-const struct nvc0_graph_init
-nvf0_graph_init_cwd_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_cwd_0[] = {
 	{ 0x405b44,   1, 0x04, 0x00000000 },
 	{ 0x405b50,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
-nvf0_graph_init_gpc_unk_1[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_gpc_unk_1[] = {
 	{ 0x418d00,   1, 0x04, 0x00000000 },
 	{ 0x418d28,   2, 0x04, 0x00000000 },
 	{ 0x418f00,   1, 0x04, 0x00000400 },
@@ -88,8 +88,8 @@ nvf0_graph_init_gpc_unk_1[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvf0_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_tex_0[] = {
 	{ 0x419ab0,   1, 0x04, 0x00000000 },
 	{ 0x419ac8,   1, 0x04, 0x00000000 },
 	{ 0x419ab8,   1, 0x04, 0x000000e7 },
@@ -100,8 +100,8 @@ nvf0_graph_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nvf0_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+nvf0_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419ca8,   1, 0x04, 0x00000000 },
 	{ 0x419cb0,   1, 0x04, 0x01000000 },
@@ -115,8 +115,8 @@ nvf0_graph_init_l1c_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
-nvf0_graph_init_sm_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000080 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ee4,   1, 0x04, 0x00000000 },
@@ -132,37 +132,37 @@ nvf0_graph_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-nvf0_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvf0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvf0_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ nvf0_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ nvf0_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvf0_gr_pack_mmio[] = {
+	{ nve4_gr_init_main_0 },
+	{ nvf0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nvf0_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvf0_gr_init_sked_0 },
+	{ nvf0_gr_init_cwd_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nvf0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nve4_gr_init_tpccs_0 },
+	{ nvf0_gr_init_tex_0 },
+	{ nve4_gr_init_pe_0 },
+	{ nvf0_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ nvf0_gr_init_sm_0 },
+	{ nvd7_gr_init_pes_0 },
+	{ nvd7_gr_init_wwdx_0 },
+	{ nvd7_gr_init_cbm_0 },
+	{ nve4_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -171,9 +171,9 @@ nvf0_graph_pack_mmio[] = {
  ******************************************************************************/
 
 int
-nvf0_graph_fini(struct nouveau_object *object, bool suspend)
+nvf0_gr_fini(struct nouveau_object *object, bool suspend)
 {
-	struct nvc0_graph_priv *priv = (void *)object;
+	struct nvc0_gr_priv *priv = (void *)object;
 	static const struct {
 		u32 addr;
 		u32 data;
@@ -204,13 +204,13 @@ nvf0_graph_fini(struct nouveau_object *object, bool suspend)
 		nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
 	}
 
-	return nouveau_graph_fini(&priv->base, suspend);
+	return nouveau_gr_fini(&priv->base, suspend);
 }
 
 #include "fuc/hubnvf0.fuc3.h"
 
-struct nvc0_graph_ucode
-nvf0_graph_fecs_ucode = {
+struct nvc0_gr_ucode
+nvf0_gr_fecs_ucode = {
 	.code.data = nvf0_grhub_code,
 	.code.size = sizeof(nvf0_grhub_code),
 	.data.data = nvf0_grhub_data,
@@ -219,8 +219,8 @@ nvf0_graph_fecs_ucode = {
 
 #include "fuc/gpcnvf0.fuc3.h"
 
-struct nvc0_graph_ucode
-nvf0_graph_gpccs_ucode = {
+struct nvc0_gr_ucode
+nvf0_gr_gpccs_ucode = {
 	.code.data = nvf0_grgpc_code,
 	.code.size = sizeof(nvf0_grgpc_code),
 	.data.data = nvf0_grgpc_data,
@@ -228,18 +228,18 @@ nvf0_graph_gpccs_ucode = {
 };
 
 struct nouveau_oclass *
-nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
+nvf0_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xf0),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nvf0_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = nvf0_gr_fini,
 	},
 	.cclass = &nvf0_grctx_oclass,
-	.sclass =  nvf0_graph_sclass,
-	.mmio = nvf0_graph_pack_mmio,
-	.fecs.ucode = &nvf0_graph_fecs_ucode,
-	.gpccs.ucode = &nvf0_graph_gpccs_ucode,
+	.sclass =  nvf0_gr_sclass,
+	.mmio = nvf0_gr_pack_mmio,
+	.fecs.ucode = &nvf0_gr_fecs_ucode,
+	.gpccs.ucode = &nvf0_gr_gpccs_ucode,
 	.ppc_nr = 2,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h

@@ -1,5 +1,5 @@
-#ifndef __NOUVEAU_GRAPH_REGS_H__
-#define __NOUVEAU_GRAPH_REGS_H__
+#ifndef __NOUVEAU_GR_REGS_H__
+#define __NOUVEAU_GR_REGS_H__
 
 #define NV04_PGRAPH_DEBUG_0                                0x00400080
 #define NV04_PGRAPH_DEBUG_1                                0x00400084

drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild

@@ -1,36 +0,0 @@
-nvkm-y += nvkm/engine/graph/ctxnv40.o
-nvkm-y += nvkm/engine/graph/ctxnv50.o
-nvkm-y += nvkm/engine/graph/ctxnvc0.o
-nvkm-y += nvkm/engine/graph/ctxnvc1.o
-nvkm-y += nvkm/engine/graph/ctxnvc4.o
-nvkm-y += nvkm/engine/graph/ctxnvc8.o
-nvkm-y += nvkm/engine/graph/ctxnvd7.o
-nvkm-y += nvkm/engine/graph/ctxnvd9.o
-nvkm-y += nvkm/engine/graph/ctxnve4.o
-nvkm-y += nvkm/engine/graph/ctxgk20a.o
-nvkm-y += nvkm/engine/graph/ctxnvf0.o
-nvkm-y += nvkm/engine/graph/ctxgk110b.o
-nvkm-y += nvkm/engine/graph/ctxnv108.o
-nvkm-y += nvkm/engine/graph/ctxgm107.o
-nvkm-y += nvkm/engine/graph/nv04.o
-nvkm-y += nvkm/engine/graph/nv10.o
-nvkm-y += nvkm/engine/graph/nv20.o
-nvkm-y += nvkm/engine/graph/nv25.o
-nvkm-y += nvkm/engine/graph/nv2a.o
-nvkm-y += nvkm/engine/graph/nv30.o
-nvkm-y += nvkm/engine/graph/nv34.o
-nvkm-y += nvkm/engine/graph/nv35.o
-nvkm-y += nvkm/engine/graph/nv40.o
-nvkm-y += nvkm/engine/graph/nv50.o
-nvkm-y += nvkm/engine/graph/nvc0.o
-nvkm-y += nvkm/engine/graph/nvc1.o
-nvkm-y += nvkm/engine/graph/nvc4.o
-nvkm-y += nvkm/engine/graph/nvc8.o
-nvkm-y += nvkm/engine/graph/nvd7.o
-nvkm-y += nvkm/engine/graph/nvd9.o
-nvkm-y += nvkm/engine/graph/nve4.o
-nvkm-y += nvkm/engine/graph/gk20a.o
-nvkm-y += nvkm/engine/graph/nvf0.o
-nvkm-y += nvkm/engine/graph/gk110b.o
-nvkm-y += nvkm/engine/graph/nv108.o
-nvkm-y += nvkm/engine/graph/gm107.o

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h

@@ -1,202 +0,0 @@
-#ifndef __NVKM_GRCTX_NVC0_H__
-#define __NVKM_GRCTX_NVC0_H__
-
-#include "nvc0.h"
-
-struct nvc0_grctx {
-	struct nvc0_graph_priv *priv;
-	struct nvc0_graph_data *data;
-	struct nvc0_graph_mmio *mmio;
-	int buffer_nr;
-	u64 buffer[4];
-	u64 addr;
-};
-
-int  nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
-void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
-
-#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
-#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
-#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
-#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c),  0, -1)
-
-struct nvc0_grctx_oclass {
-	struct nouveau_oclass base;
-	/* main context generation function */
-	void  (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
-	/* context-specific modify-on-first-load list generation function */
-	void  (*unkn)(struct nvc0_graph_priv *);
-	/* mmio context data */
-	const struct nvc0_graph_pack *hub;
-	const struct nvc0_graph_pack *gpc;
-	const struct nvc0_graph_pack *zcull;
-	const struct nvc0_graph_pack *tpc;
-	const struct nvc0_graph_pack *ppc;
-	/* indirect context data, generated with icmds/mthds */
-	const struct nvc0_graph_pack *icmd;
-	const struct nvc0_graph_pack *mthd;
-	/* bundle circular buffer */
-	void (*bundle)(struct nvc0_grctx *);
-	u32 bundle_size;
-	u32 bundle_min_gpm_fifo_depth;
-	u32 bundle_token_limit;
-	/* pagepool */
-	void (*pagepool)(struct nvc0_grctx *);
-	u32 pagepool_size;
-	/* attribute(/alpha) circular buffer */
-	void (*attrib)(struct nvc0_grctx *);
-	u32 attrib_nr_max;
-	u32 attrib_nr;
-	u32 alpha_nr_max;
-	u32 alpha_nr;
-};
-
-static inline const struct nvc0_grctx_oclass *
-nvc0_grctx_impl(struct nvc0_graph_priv *priv)
-{
-	return (void *)nv_engine(priv)->cclass;
-}
-
-extern struct nouveau_oclass *nvc0_grctx_oclass;
-int  nvc0_grctx_generate(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
-void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
-void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvc1_grctx_oclass;
-void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvc4_grctx_oclass;
-extern struct nouveau_oclass *nvc8_grctx_oclass;
-
-extern struct nouveau_oclass *nvd7_grctx_oclass;
-void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
-
-extern struct nouveau_oclass *nvd9_grctx_oclass;
-
-extern struct nouveau_oclass *nve4_grctx_oclass;
-extern struct nouveau_oclass *gk20a_grctx_oclass;
-void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nve4_grctx_generate_bundle(struct nvc0_grctx *);
-void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
-void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
-void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvf0_grctx_oclass;
-extern struct nouveau_oclass *gk110b_grctx_oclass;
-extern struct nouveau_oclass *nv108_grctx_oclass;
-extern struct nouveau_oclass *gm107_grctx_oclass;
-
-/* context init value lists */
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[];
-extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[];
-extern const struct nvc0_graph_init nvc0_grctx_init_main_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
-extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[];
-
-extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[];
-extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[];
-extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[];
-extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[];
-
-extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];
-extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
-
-extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[];
-extern const struct nvc0_graph_init nvd9_grctx_init_be_0[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[];
-
-extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[];
-
-extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];
-extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];
-extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_pes_0[];
-
-extern const struct nvc0_graph_pack nve4_grctx_pack_hub[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[];
-extern const struct nvc0_graph_init nve4_grctx_init_a097_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_hub[];
-extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_gpc[];
-extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[];
-
-extern const struct nvc0_graph_init nvf0_grctx_init_tex_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_ppc[];
-
-extern const struct nvc0_graph_init nv108_grctx_init_rstr2d_0[];
-
-extern const struct nvc0_graph_init nv108_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nv108_grctx_init_crstr_0[];
-
-
-#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h

@@ -1,31 +0,0 @@
-#ifndef __NV20_GRAPH_H__
-#define __NV20_GRAPH_H__
-
-#include <core/enum.h>
-
-#include <engine/graph.h>
-#include <engine/fifo.h>
-
-struct nv20_graph_priv {
-	struct nouveau_graph base;
-	struct nouveau_gpuobj *ctxtab;
-};
-
-struct nv20_graph_chan {
-	struct nouveau_graph_chan base;
-	int chid;
-};
-
-extern struct nouveau_oclass nv25_graph_sclass[];
-int  nv20_graph_context_init(struct nouveau_object *);
-int  nv20_graph_context_fini(struct nouveau_object *, bool);
-
-void nv20_graph_tile_prog(struct nouveau_engine *, int);
-void nv20_graph_intr(struct nouveau_subdev *);
-
-void nv20_graph_dtor(struct nouveau_object *);
-int  nv20_graph_init(struct nouveau_object *);
-
-int  nv30_graph_init(struct nouveau_object *);
-
-#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h

@@ -1,270 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NVC0_GRAPH_H__
-#define __NVC0_GRAPH_H__
-
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-#include <subdev/mc.h>
-#include <subdev/ltc.h>
-
-#include <engine/fifo.h>
-#include <engine/graph.h>
-
-#include "fuc/os.h"
-
-#define GPC_MAX 32
-#define TPC_MAX (GPC_MAX * 8)
-
-#define ROP_BCAST(r)      (0x408800 + (r))
-#define ROP_UNIT(u, r)    (0x410000 + (u) * 0x400 + (r))
-#define GPC_BCAST(r)      (0x418000 + (r))
-#define GPC_UNIT(t, r)    (0x500000 + (t) * 0x8000 + (r))
-#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
-#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
-
-struct nvc0_graph_data {
-	u32 size;
-	u32 align;
-	u32 access;
-};
-
-struct nvc0_graph_mmio {
-	u32 addr;
-	u32 data;
-	u32 shift;
-	int buffer;
-};
-
-struct nvc0_graph_fuc {
-	u32 *data;
-	u32  size;
-};
-
-struct nvc0_graph_zbc_color {
-	u32 format;
-	u32 ds[4];
-	u32 l2[4];
-};
-
-struct nvc0_graph_zbc_depth {
-	u32 format;
-	u32 ds;
-	u32 l2;
-};
-
-struct nvc0_graph_priv {
-	struct nouveau_graph base;
-
-	struct nvc0_graph_fuc fuc409c;
-	struct nvc0_graph_fuc fuc409d;
-	struct nvc0_graph_fuc fuc41ac;
-	struct nvc0_graph_fuc fuc41ad;
-	bool firmware;
-
-	struct nvc0_graph_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT];
-	struct nvc0_graph_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
-
-	u8 rop_nr;
-	u8 gpc_nr;
-	u8 tpc_nr[GPC_MAX];
-	u8 tpc_total;
-	u8 ppc_nr[GPC_MAX];
-	u8 ppc_tpc_nr[GPC_MAX][4];
-
-	struct nouveau_gpuobj *unk4188b4;
-	struct nouveau_gpuobj *unk4188b8;
-
-	struct nvc0_graph_data mmio_data[4];
-	struct nvc0_graph_mmio mmio_list[4096/8];
-	u32  size;
-	u32 *data;
-
-	u8 magic_not_rop_nr;
-};
-
-struct nvc0_graph_chan {
-	struct nouveau_graph_chan base;
-
-	struct nouveau_gpuobj *mmio;
-	struct nouveau_vma mmio_vma;
-	int mmio_nr;
-	struct {
-		struct nouveau_gpuobj *mem;
-		struct nouveau_vma vma;
-	} data[4];
-};
-
-int  nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
-			     struct nouveau_oclass *, void *, u32,
-			     struct nouveau_object **);
-void nvc0_graph_context_dtor(struct nouveau_object *);
-
-void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
-
-u64  nvc0_graph_units(struct nouveau_graph *);
-int  nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *,
-		     struct nouveau_oclass *, void *data, u32 size,
-		     struct nouveau_object **);
-void nvc0_graph_dtor(struct nouveau_object *);
-int  nvc0_graph_init(struct nouveau_object *);
-void nvc0_graph_zbc_init(struct nvc0_graph_priv *);
-
-int  nve4_graph_fini(struct nouveau_object *, bool);
-int  nve4_graph_init(struct nouveau_object *);
-
-int  nvf0_graph_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
-
-extern struct nouveau_oclass nvc0_graph_sclass[];
-extern struct nouveau_omthds nvc0_graph_9097_omthds[];
-extern struct nouveau_omthds nvc0_graph_90c0_omthds[];
-extern struct nouveau_oclass nvc8_graph_sclass[];
-extern struct nouveau_oclass nvf0_graph_sclass[];
-
-struct nvc0_graph_init {
-	u32 addr;
-	u8  count;
-	u8  pitch;
-	u32 data;
-};
-
-struct nvc0_graph_pack {
-	const struct nvc0_graph_init *init;
-	u32 type;
-};
-
-#define pack_for_each_init(init, pack, head)                                   \
-	for (pack = head; pack && pack->init; pack++)                          \
-		  for (init = pack->init; init && init->count; init++)
-
-struct nvc0_graph_ucode {
-	struct nvc0_graph_fuc code;
-	struct nvc0_graph_fuc data;
-};
-
-extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode;
-extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode;
-
-extern struct nvc0_graph_ucode nvf0_graph_fecs_ucode;
-extern struct nvc0_graph_ucode nvf0_graph_gpccs_ucode;
-
-struct nvc0_graph_oclass {
-	struct nouveau_oclass base;
-	struct nouveau_oclass **cclass;
-	struct nouveau_oclass *sclass;
-	const struct nvc0_graph_pack *mmio;
-	struct {
-		struct nvc0_graph_ucode *ucode;
-	} fecs;
-	struct {
-		struct nvc0_graph_ucode *ucode;
-	} gpccs;
-	int ppc_nr;
-};
-
-void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-int  nvc0_graph_init_ctxctl(struct nvc0_graph_priv *);
-
-/* register init value lists */
-
-extern const struct nvc0_graph_init nvc0_graph_init_main_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_fe_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pri_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pd_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_scc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_prop_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_setup_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_crstr_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_setup_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pe_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_be_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_fe_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_pe_1[];
-
-extern const struct nvc0_graph_init nvc4_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvc4_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvc4_graph_init_sm_0[];
-
-extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc1_graph_init_setup_1[];
-
-extern const struct nvc0_graph_init nvd9_graph_init_pd_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_prop_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvd9_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_sm_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_fe_1[];
-
-extern const struct nvc0_graph_init nvd7_graph_init_pes_0[];
-extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[];
-extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[];
-
-extern const struct nvc0_graph_init nve4_graph_init_main_0[];
-extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[];
-extern const struct nvc0_graph_init nve4_graph_init_pe_0[];
-extern const struct nvc0_graph_init nve4_graph_init_be_0[];
-extern const struct nvc0_graph_pack nve4_graph_pack_mmio[];
-
-extern const struct nvc0_graph_init nvf0_graph_init_fe_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_sked_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvf0_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_sm_0[];
-
-extern const struct nvc0_graph_init nv108_graph_init_gpc_unk_0[];
-
-
-#endif

drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c

@@ -22,7 +22,7 @@
  * Authors: Ben Skeggs
  */
 
-#include <engine/graph/nv40.h>
+#include <engine/gr/nv40.h>
 
 #include "nv04.h"
 
@@ -73,12 +73,12 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 
 	/* PRAMIN aperture maps over the end of vram, reserve enough space
 	 * to fit graphics contexts for every channel, the magics come
-	 * from engine/graph/nv40.c
+	 * from engine/gr/nv40.c
 	 */
 	vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8);
 	if      (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs;
 	else if (device->chipset  < 0x43) priv->base.reserved = 0x4f00 * vs;
-	else if (nv44_graph_class(priv))  priv->base.reserved = 0x4980 * vs;
+	else if (nv44_gr_class(priv))  priv->base.reserved = 0x4980 * vs;
 	else				  priv->base.reserved = 0x4a40 * vs;
 	priv->base.reserved += 16 * 1024;
 	priv->base.reserved *= 32;		/* per-channel */