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@@ -14,8 +14,12 @@
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*
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*/
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+#include <linux/atomic.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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+#include <linux/dmaengine.h>
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+#include <linux/dmapool.h>
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+#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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@@ -24,6 +28,7 @@
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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+#include <linux/scatterlist.h>
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/* QUP Registers */
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#define QUP_CONFIG 0x000
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@@ -33,6 +38,7 @@
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#define QUP_OPERATIONAL 0x018
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#define QUP_ERROR_FLAGS 0x01c
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#define QUP_ERROR_FLAGS_EN 0x020
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+#define QUP_OPERATIONAL_MASK 0x028
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#define QUP_HW_VERSION 0x030
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#define QUP_MX_OUTPUT_CNT 0x100
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#define QUP_OUT_FIFO_BASE 0x110
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@@ -42,6 +48,7 @@
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#define QUP_IN_FIFO_BASE 0x218
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#define QUP_I2C_CLK_CTL 0x400
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#define QUP_I2C_STATUS 0x404
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+#define QUP_I2C_MASTER_GEN 0x408
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/* QUP States and reset values */
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#define QUP_RESET_STATE 0
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@@ -51,6 +58,7 @@
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#define QUP_STATE_VALID BIT(2)
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#define QUP_I2C_MAST_GEN BIT(4)
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+#define QUP_I2C_FLUSH BIT(6)
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#define QUP_OPERATIONAL_RESET 0x000ff0
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#define QUP_I2C_STATUS_RESET 0xfffffc
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@@ -69,16 +77,22 @@
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#define QUP_CLOCK_AUTO_GATE BIT(13)
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#define I2C_MINI_CORE (2 << 8)
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#define I2C_N_VAL 15
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+#define I2C_N_VAL_V2 7
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+
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/* Most significant word offset in FIFO port */
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#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
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/* Packing/Unpacking words in FIFOs, and IO modes */
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#define QUP_OUTPUT_BLK_MODE (1 << 10)
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+#define QUP_OUTPUT_BAM_MODE (3 << 10)
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#define QUP_INPUT_BLK_MODE (1 << 12)
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+#define QUP_INPUT_BAM_MODE (3 << 12)
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+#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
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#define QUP_UNPACK_EN BIT(14)
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#define QUP_PACK_EN BIT(15)
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#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
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+#define QUP_V2_TAGS_EN 1
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#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
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#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
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@@ -90,6 +104,15 @@
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#define QUP_TAG_DATA (2 << 8)
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#define QUP_TAG_STOP (3 << 8)
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#define QUP_TAG_REC (4 << 8)
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+#define QUP_BAM_INPUT_EOT 0x93
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+#define QUP_BAM_FLUSH_STOP 0x96
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+
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+/* QUP v2 tags */
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+#define QUP_TAG_V2_START 0x81
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+#define QUP_TAG_V2_DATAWR 0x82
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+#define QUP_TAG_V2_DATAWR_STOP 0x83
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+#define QUP_TAG_V2_DATARD 0x85
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+#define QUP_TAG_V2_DATARD_STOP 0x87
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/* Status, Error flags */
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#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
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@@ -98,6 +121,36 @@
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#define QUP_STATUS_ERROR_FLAGS 0x7c
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#define QUP_READ_LIMIT 256
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+#define SET_BIT 0x1
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+#define RESET_BIT 0x0
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+#define ONE_BYTE 0x1
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+#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
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+
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+#define MX_TX_RX_LEN SZ_64K
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+#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
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+
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+/* Max timeout in ms for 32k bytes */
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+#define TOUT_MAX 300
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+
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+struct qup_i2c_block {
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+ int count;
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+ int pos;
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+ int tx_tag_len;
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+ int rx_tag_len;
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+ int data_len;
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+ u8 tags[6];
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+};
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+
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+struct qup_i2c_tag {
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+ u8 *start;
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+ dma_addr_t addr;
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+};
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+
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+struct qup_i2c_bam {
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+ struct qup_i2c_tag tag;
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+ struct dma_chan *dma;
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+ struct scatterlist *sg;
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+};
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struct qup_i2c_dev {
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struct device *dev;
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@@ -114,6 +167,7 @@ struct qup_i2c_dev {
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int in_blk_sz;
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unsigned long one_byte_t;
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+ struct qup_i2c_block blk;
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struct i2c_msg *msg;
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/* Current posion in user message buffer */
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@@ -123,6 +177,19 @@ struct qup_i2c_dev {
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/* QUP core errors */
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u32 qup_err;
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+ /* To check if this is the last msg */
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+ bool is_last;
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+
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+ /* To configure when bus is in run state */
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+ int config_run;
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+
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+ /* dma parameters */
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+ bool is_dma;
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+ struct dma_pool *dpool;
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+ struct qup_i2c_tag start_tag;
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+ struct qup_i2c_bam brx;
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+ struct qup_i2c_bam btx;
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+
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struct completion xfer;
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};
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@@ -199,6 +266,14 @@ static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
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return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
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}
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+static void qup_i2c_flush(struct qup_i2c_dev *qup)
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+{
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+ u32 val = readl(qup->base + QUP_STATE);
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+
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+ val |= QUP_I2C_FLUSH;
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+ writel(val, qup->base + QUP_STATE);
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+}
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+
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static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
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{
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return qup_i2c_poll_state_mask(qup, 0, 0);
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@@ -221,26 +296,62 @@ static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
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return 0;
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}
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-static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)
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+/**
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+ * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
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+ * @qup: The qup_i2c_dev device
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+ * @op: The bit/event to wait on
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+ * @val: value of the bit to wait on, 0 or 1
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+ * @len: The length the bytes to be transferred
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+ */
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+static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
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+ int len)
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{
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unsigned long timeout;
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u32 opflags;
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u32 status;
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+ u32 shift = __ffs(op);
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- timeout = jiffies + HZ;
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+ len *= qup->one_byte_t;
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+ /* timeout after a wait of twice the max time */
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+ timeout = jiffies + len * 4;
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for (;;) {
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opflags = readl(qup->base + QUP_OPERATIONAL);
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status = readl(qup->base + QUP_I2C_STATUS);
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- if (!(opflags & QUP_OUT_NOT_EMPTY) &&
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- !(status & I2C_STATUS_BUS_ACTIVE))
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- return 0;
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+ if (((opflags & op) >> shift) == val) {
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+ if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
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+ if (!(status & I2C_STATUS_BUS_ACTIVE))
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+ return 0;
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+ } else {
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+ return 0;
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+ }
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+ }
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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- usleep_range(qup->one_byte_t, qup->one_byte_t * 2);
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+ usleep_range(len, len * 2);
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+ }
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+}
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+
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+static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
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+ struct i2c_msg *msg)
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+{
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+ /* Number of entries to shift out, including the tags */
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+ int total = msg->len + qup->blk.tx_tag_len;
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+
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+ total |= qup->config_run;
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+
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+ if (total < qup->out_fifo_sz) {
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+ /* FIFO mode */
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+ writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
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+ writel(total, qup->base + QUP_MX_WRITE_CNT);
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+ } else {
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+ /* BLOCK mode (transfer data on chunks) */
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+ writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
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+ qup->base + QUP_IO_MODE);
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+ writel(total, qup->base + QUP_MX_OUTPUT_CNT);
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}
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}
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@@ -261,13 +372,45 @@ static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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}
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}
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-static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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+static int check_for_fifo_space(struct qup_i2c_dev *qup)
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+{
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+ int ret;
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+
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+ ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
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+ if (ret)
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+ goto out;
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+
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+ ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
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+ RESET_BIT, 4 * ONE_BYTE);
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+ if (ret) {
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+ /* Fifo is full. Drain out the fifo */
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+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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+ if (ret)
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+ goto out;
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+
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+ ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY,
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+ RESET_BIT, 256 * ONE_BYTE);
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+ if (ret) {
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+ dev_err(qup->dev, "timeout for fifo out full");
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+ goto out;
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+ }
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+
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+ ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
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+ if (ret)
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+ goto out;
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+ }
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+
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+out:
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+ return ret;
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+}
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+
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+static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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u32 addr = msg->addr << 1;
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u32 qup_tag;
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- u32 opflags;
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int idx;
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u32 val;
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+ int ret = 0;
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if (qup->pos == 0) {
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val = QUP_TAG_START | addr;
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@@ -279,9 +422,9 @@ static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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while (qup->pos < msg->len) {
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/* Check that there's space in the FIFO for our pair */
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- opflags = readl(qup->base + QUP_OPERATIONAL);
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- if (opflags & QUP_OUT_FULL)
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- break;
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+ ret = check_for_fifo_space(qup);
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+ if (ret)
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+ return ret;
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if (qup->pos == msg->len - 1)
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qup_tag = QUP_TAG_STOP;
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@@ -300,11 +443,501 @@ static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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qup->pos++;
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idx++;
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}
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+
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+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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+
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+ return ret;
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}
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-static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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+static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
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+ struct i2c_msg *msg)
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+{
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+ memset(&qup->blk, 0, sizeof(qup->blk));
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+
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+ qup->blk.data_len = msg->len;
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+ qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
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+
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+ /* 4 bytes for first block and 2 writes for rest */
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+ qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
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+
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+ /* There are 2 tag bytes that are read in to fifo for every block */
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+ if (msg->flags & I2C_M_RD)
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+ qup->blk.rx_tag_len = qup->blk.count * 2;
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+}
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+
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+static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
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+ int dlen, u8 *dbuf)
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+{
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+ u32 val = 0, idx = 0, pos = 0, i = 0, t;
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+ int len = tlen + dlen;
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+ u8 *buf = tbuf;
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+ int ret = 0;
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+
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+ while (len > 0) {
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+ ret = check_for_fifo_space(qup);
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+ if (ret)
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+ return ret;
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+
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+ t = (len >= 4) ? 4 : len;
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+
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+ while (idx < t) {
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+ if (!i && (pos >= tlen)) {
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+ buf = dbuf;
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+ pos = 0;
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+ i = 1;
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+ }
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+ val |= buf[pos++] << (idx++ * 8);
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+ }
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+
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+ writel(val, qup->base + QUP_OUT_FIFO_BASE);
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+ idx = 0;
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+ val = 0;
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+ len -= 4;
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+ }
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+
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+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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+
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+ return ret;
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+}
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+
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+static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
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+{
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+ int data_len;
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+
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+ if (qup->blk.data_len > QUP_READ_LIMIT)
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+ data_len = QUP_READ_LIMIT;
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+ else
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+ data_len = qup->blk.data_len;
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+
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+ return data_len;
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+}
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+
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+static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
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+ struct i2c_msg *msg, int is_dma)
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+{
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+ u16 addr = (msg->addr << 1) | ((msg->flags & I2C_M_RD) == I2C_M_RD);
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+ int len = 0;
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+ int data_len;
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+
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+ int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
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+
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+ if (qup->blk.pos == 0) {
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+ tags[len++] = QUP_TAG_V2_START;
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+ tags[len++] = addr & 0xff;
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+
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+ if (msg->flags & I2C_M_TEN)
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+ tags[len++] = addr >> 8;
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+ }
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+
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+ /* Send _STOP commands for the last block */
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+ if (last) {
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+ if (msg->flags & I2C_M_RD)
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+ tags[len++] = QUP_TAG_V2_DATARD_STOP;
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+ else
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+ tags[len++] = QUP_TAG_V2_DATAWR_STOP;
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+ } else {
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|
|
+ if (msg->flags & I2C_M_RD)
|
|
|
+ tags[len++] = QUP_TAG_V2_DATARD;
|
|
|
+ else
|
|
|
+ tags[len++] = QUP_TAG_V2_DATAWR;
|
|
|
+ }
|
|
|
+
|
|
|
+ data_len = qup_i2c_get_data_len(qup);
|
|
|
+
|
|
|
+ /* 0 implies 256 bytes */
|
|
|
+ if (data_len == QUP_READ_LIMIT)
|
|
|
+ tags[len++] = 0;
|
|
|
+ else
|
|
|
+ tags[len++] = data_len;
|
|
|
+
|
|
|
+ if ((msg->flags & I2C_M_RD) && last && is_dma) {
|
|
|
+ tags[len++] = QUP_BAM_INPUT_EOT;
|
|
|
+ tags[len++] = QUP_BAM_FLUSH_STOP;
|
|
|
+ }
|
|
|
+
|
|
|
+ return len;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
+{
|
|
|
+ int data_len = 0, tag_len, index;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
|
|
|
+ index = msg->len - qup->blk.data_len;
|
|
|
+
|
|
|
+ /* only tags are written for read */
|
|
|
+ if (!(msg->flags & I2C_M_RD))
|
|
|
+ data_len = qup_i2c_get_data_len(qup);
|
|
|
+
|
|
|
+ ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
|
|
|
+ data_len, &msg->buf[index]);
|
|
|
+ qup->blk.data_len -= data_len;
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void qup_i2c_bam_cb(void *data)
|
|
|
+{
|
|
|
+ struct qup_i2c_dev *qup = data;
|
|
|
+
|
|
|
+ complete(&qup->xfer);
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
|
|
|
+ struct qup_i2c_tag *tg, unsigned int buflen,
|
|
|
+ struct qup_i2c_dev *qup, int map, int dir)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ sg_set_buf(sg, buf, buflen);
|
|
|
+ ret = dma_map_sg(qup->dev, sg, 1, dir);
|
|
|
+ if (!ret)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ if (!map)
|
|
|
+ sg_dma_address(sg) = tg->addr + ((u8 *)buf - tg->start);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
|
|
|
+{
|
|
|
+ if (qup->btx.dma)
|
|
|
+ dma_release_channel(qup->btx.dma);
|
|
|
+ if (qup->brx.dma)
|
|
|
+ dma_release_channel(qup->brx.dma);
|
|
|
+ qup->btx.dma = NULL;
|
|
|
+ qup->brx.dma = NULL;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
|
|
|
+{
|
|
|
+ int err;
|
|
|
+
|
|
|
+ if (!qup->btx.dma) {
|
|
|
+ qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
|
|
|
+ if (IS_ERR(qup->btx.dma)) {
|
|
|
+ err = PTR_ERR(qup->btx.dma);
|
|
|
+ qup->btx.dma = NULL;
|
|
|
+ dev_err(qup->dev, "\n tx channel not available");
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!qup->brx.dma) {
|
|
|
+ qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
|
|
|
+ if (IS_ERR(qup->brx.dma)) {
|
|
|
+ dev_err(qup->dev, "\n rx channel not available");
|
|
|
+ err = PTR_ERR(qup->brx.dma);
|
|
|
+ qup->brx.dma = NULL;
|
|
|
+ qup_i2c_rel_dma(qup);
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg,
|
|
|
+ int num)
|
|
|
+{
|
|
|
+ struct dma_async_tx_descriptor *txd, *rxd = NULL;
|
|
|
+ int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
|
|
|
+ dma_cookie_t cookie_rx, cookie_tx;
|
|
|
+ u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
|
|
|
+ u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
|
|
|
+ u8 *tags;
|
|
|
+
|
|
|
+ while (idx < num) {
|
|
|
+ blocks = (msg->len + limit) / limit;
|
|
|
+ rem = msg->len % limit;
|
|
|
+ tx_len = 0, len = 0, i = 0;
|
|
|
+
|
|
|
+ qup->is_last = (idx == (num - 1));
|
|
|
+
|
|
|
+ qup_i2c_set_blk_data(qup, msg);
|
|
|
+
|
|
|
+ if (msg->flags & I2C_M_RD) {
|
|
|
+ rx_nents += (blocks * 2) + 1;
|
|
|
+ tx_nents += 1;
|
|
|
+
|
|
|
+ while (qup->blk.pos < blocks) {
|
|
|
+ /* length set to '0' implies 256 bytes */
|
|
|
+ tlen = (i == (blocks - 1)) ? rem : 0;
|
|
|
+ tags = &qup->start_tag.start[off + len];
|
|
|
+ len += qup_i2c_set_tags(tags, qup, msg, 1);
|
|
|
+
|
|
|
+ /* scratch buf to read the start and len tags */
|
|
|
+ ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
|
|
|
+ &qup->brx.tag.start[0],
|
|
|
+ &qup->brx.tag,
|
|
|
+ 2, qup, 0, 0);
|
|
|
+
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
|
|
|
+ &msg->buf[limit * i],
|
|
|
+ NULL, tlen, qup,
|
|
|
+ 1, DMA_FROM_DEVICE);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ i++;
|
|
|
+ qup->blk.pos = i;
|
|
|
+ }
|
|
|
+ ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
|
|
|
+ &qup->start_tag.start[off],
|
|
|
+ &qup->start_tag, len, qup, 0, 0);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ off += len;
|
|
|
+ /* scratch buf to read the BAM EOT and FLUSH tags */
|
|
|
+ ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
|
|
|
+ &qup->brx.tag.start[0],
|
|
|
+ &qup->brx.tag, 2,
|
|
|
+ qup, 0, 0);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ } else {
|
|
|
+ tx_nents += (blocks * 2);
|
|
|
+
|
|
|
+ while (qup->blk.pos < blocks) {
|
|
|
+ tlen = (i == (blocks - 1)) ? rem : 0;
|
|
|
+ tags = &qup->start_tag.start[off + tx_len];
|
|
|
+ len = qup_i2c_set_tags(tags, qup, msg, 1);
|
|
|
+
|
|
|
+ ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
|
|
|
+ tags,
|
|
|
+ &qup->start_tag, len,
|
|
|
+ qup, 0, 0);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ tx_len += len;
|
|
|
+ ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
|
|
|
+ &msg->buf[limit * i],
|
|
|
+ NULL, tlen, qup, 1,
|
|
|
+ DMA_TO_DEVICE);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ i++;
|
|
|
+ qup->blk.pos = i;
|
|
|
+ }
|
|
|
+ off += tx_len;
|
|
|
+
|
|
|
+ if (idx == (num - 1)) {
|
|
|
+ len = 1;
|
|
|
+ if (rx_nents) {
|
|
|
+ qup->btx.tag.start[0] =
|
|
|
+ QUP_BAM_INPUT_EOT;
|
|
|
+ len++;
|
|
|
+ }
|
|
|
+ qup->btx.tag.start[len - 1] =
|
|
|
+ QUP_BAM_FLUSH_STOP;
|
|
|
+ ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
|
|
|
+ &qup->btx.tag.start[0],
|
|
|
+ &qup->btx.tag, len,
|
|
|
+ qup, 0, 0);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ tx_nents += 1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ idx++;
|
|
|
+ msg++;
|
|
|
+ }
|
|
|
+
|
|
|
+ txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
|
|
|
+ DMA_MEM_TO_DEV,
|
|
|
+ DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
|
|
|
+ if (!txd) {
|
|
|
+ dev_err(qup->dev, "failed to get tx desc\n");
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto desc_err;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!rx_nents) {
|
|
|
+ txd->callback = qup_i2c_bam_cb;
|
|
|
+ txd->callback_param = qup;
|
|
|
+ }
|
|
|
+
|
|
|
+ cookie_tx = dmaengine_submit(txd);
|
|
|
+ if (dma_submit_error(cookie_tx)) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto desc_err;
|
|
|
+ }
|
|
|
+
|
|
|
+ dma_async_issue_pending(qup->btx.dma);
|
|
|
+
|
|
|
+ if (rx_nents) {
|
|
|
+ rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
|
|
|
+ rx_nents, DMA_DEV_TO_MEM,
|
|
|
+ DMA_PREP_INTERRUPT);
|
|
|
+ if (!rxd) {
|
|
|
+ dev_err(qup->dev, "failed to get rx desc\n");
|
|
|
+ ret = -EINVAL;
|
|
|
+
|
|
|
+ /* abort TX descriptors */
|
|
|
+ dmaengine_terminate_all(qup->btx.dma);
|
|
|
+ goto desc_err;
|
|
|
+ }
|
|
|
+
|
|
|
+ rxd->callback = qup_i2c_bam_cb;
|
|
|
+ rxd->callback_param = qup;
|
|
|
+ cookie_rx = dmaengine_submit(rxd);
|
|
|
+ if (dma_submit_error(cookie_rx)) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto desc_err;
|
|
|
+ }
|
|
|
+
|
|
|
+ dma_async_issue_pending(qup->brx.dma);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
|
|
|
+ dev_err(qup->dev, "normal trans timed out\n");
|
|
|
+ ret = -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ret || qup->bus_err || qup->qup_err) {
|
|
|
+ if (qup->bus_err & QUP_I2C_NACK_FLAG) {
|
|
|
+ msg--;
|
|
|
+ dev_err(qup->dev, "NACK from %x\n", msg->addr);
|
|
|
+ ret = -EIO;
|
|
|
+
|
|
|
+ if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
|
|
|
+ dev_err(qup->dev, "change to run state timed out");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (rx_nents)
|
|
|
+ writel(QUP_BAM_INPUT_EOT,
|
|
|
+ qup->base + QUP_OUT_FIFO_BASE);
|
|
|
+
|
|
|
+ writel(QUP_BAM_FLUSH_STOP,
|
|
|
+ qup->base + QUP_OUT_FIFO_BASE);
|
|
|
+
|
|
|
+ qup_i2c_flush(qup);
|
|
|
+
|
|
|
+ /* wait for remaining interrupts to occur */
|
|
|
+ if (!wait_for_completion_timeout(&qup->xfer, HZ))
|
|
|
+ dev_err(qup->dev, "flush timed out\n");
|
|
|
+
|
|
|
+ qup_i2c_rel_dma(qup);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
|
|
|
+
|
|
|
+ if (rx_nents)
|
|
|
+ dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
|
|
|
+ DMA_FROM_DEVICE);
|
|
|
+desc_err:
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
|
|
|
+ int num)
|
|
|
+{
|
|
|
+ struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ enable_irq(qup->irq);
|
|
|
+ ret = qup_i2c_req_dma(qup);
|
|
|
+
|
|
|
+ if (ret)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ qup->bus_err = 0;
|
|
|
+ qup->qup_err = 0;
|
|
|
+
|
|
|
+ writel(0, qup->base + QUP_MX_INPUT_CNT);
|
|
|
+ writel(0, qup->base + QUP_MX_OUTPUT_CNT);
|
|
|
+
|
|
|
+ /* set BAM mode */
|
|
|
+ writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
|
|
|
+
|
|
|
+ /* mask fifo irqs */
|
|
|
+ writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
|
|
|
+
|
|
|
+ /* set RUN STATE */
|
|
|
+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
+ if (ret)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
|
|
|
+
|
|
|
+ qup->msg = msg;
|
|
|
+ ret = qup_i2c_bam_do_xfer(qup, qup->msg, num);
|
|
|
+out:
|
|
|
+ disable_irq(qup->irq);
|
|
|
+
|
|
|
+ qup->msg = NULL;
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
|
|
|
+ struct i2c_msg *msg)
|
|
|
{
|
|
|
unsigned long left;
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ left = wait_for_completion_timeout(&qup->xfer, HZ);
|
|
|
+ if (!left) {
|
|
|
+ writel(1, qup->base + QUP_SW_RESET);
|
|
|
+ ret = -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (qup->bus_err || qup->qup_err) {
|
|
|
+ if (qup->bus_err & QUP_I2C_NACK_FLAG) {
|
|
|
+ dev_err(qup->dev, "NACK from %x\n", msg->addr);
|
|
|
+ ret = -EIO;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
+{
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ qup->msg = msg;
|
|
|
+ qup->pos = 0;
|
|
|
+ enable_irq(qup->irq);
|
|
|
+ qup_i2c_set_blk_data(qup, msg);
|
|
|
+ qup_i2c_set_write_mode_v2(qup, msg);
|
|
|
+
|
|
|
+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
|
|
|
+
|
|
|
+ do {
|
|
|
+ ret = qup_i2c_issue_xfer_v2(qup, msg);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ ret = qup_i2c_wait_for_complete(qup, msg);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ qup->blk.pos++;
|
|
|
+ } while (qup->blk.pos < qup->blk.count);
|
|
|
+
|
|
|
+ ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
|
|
|
+
|
|
|
+err:
|
|
|
+ disable_irq(qup->irq);
|
|
|
+ qup->msg = NULL;
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
+{
|
|
|
int ret;
|
|
|
|
|
|
qup->msg = msg;
|
|
|
@@ -325,30 +958,21 @@ static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
if (ret)
|
|
|
goto err;
|
|
|
|
|
|
- qup_i2c_issue_write(qup, msg);
|
|
|
-
|
|
|
- ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
+ ret = qup_i2c_issue_write(qup, msg);
|
|
|
if (ret)
|
|
|
goto err;
|
|
|
|
|
|
- left = wait_for_completion_timeout(&qup->xfer, HZ);
|
|
|
- if (!left) {
|
|
|
- writel(1, qup->base + QUP_SW_RESET);
|
|
|
- ret = -ETIMEDOUT;
|
|
|
+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
+ if (ret)
|
|
|
goto err;
|
|
|
- }
|
|
|
|
|
|
- if (qup->bus_err || qup->qup_err) {
|
|
|
- if (qup->bus_err & QUP_I2C_NACK_FLAG)
|
|
|
- dev_err(qup->dev, "NACK from %x\n", msg->addr);
|
|
|
- ret = -EIO;
|
|
|
+ ret = qup_i2c_wait_for_complete(qup, msg);
|
|
|
+ if (ret)
|
|
|
goto err;
|
|
|
- }
|
|
|
} while (qup->pos < msg->len);
|
|
|
|
|
|
/* Wait for the outstanding data in the fifo to drain */
|
|
|
- ret = qup_i2c_wait_writeready(qup);
|
|
|
-
|
|
|
+ ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
|
|
|
err:
|
|
|
disable_irq(qup->irq);
|
|
|
qup->msg = NULL;
|
|
|
@@ -370,6 +994,28 @@ static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
|
|
|
+{
|
|
|
+ int tx_len = qup->blk.tx_tag_len;
|
|
|
+
|
|
|
+ len += qup->blk.rx_tag_len;
|
|
|
+ len |= qup->config_run;
|
|
|
+ tx_len |= qup->config_run;
|
|
|
+
|
|
|
+ if (len < qup->in_fifo_sz) {
|
|
|
+ /* FIFO mode */
|
|
|
+ writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
|
|
|
+ writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
|
|
|
+ writel(len, qup->base + QUP_MX_READ_CNT);
|
|
|
+ } else {
|
|
|
+ /* BLOCK mode (transfer data on chunks) */
|
|
|
+ writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
|
|
|
+ qup->base + QUP_IO_MODE);
|
|
|
+ writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
|
|
|
+ writel(len, qup->base + QUP_MX_INPUT_CNT);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
{
|
|
|
u32 addr, len, val;
|
|
|
@@ -384,18 +1030,19 @@ static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
}
|
|
|
|
|
|
|
|
|
-static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
+static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
{
|
|
|
- u32 opflags;
|
|
|
u32 val = 0;
|
|
|
int idx;
|
|
|
+ int ret = 0;
|
|
|
|
|
|
for (idx = 0; qup->pos < msg->len; idx++) {
|
|
|
if ((idx & 1) == 0) {
|
|
|
/* Check that FIFO have data */
|
|
|
- opflags = readl(qup->base + QUP_OPERATIONAL);
|
|
|
- if (!(opflags & QUP_IN_NOT_EMPTY))
|
|
|
- break;
|
|
|
+ ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
|
|
|
+ SET_BIT, 4 * ONE_BYTE);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
|
|
|
/* Reading 2 words at time */
|
|
|
val = readl(qup->base + QUP_IN_FIFO_BASE);
|
|
|
@@ -405,18 +1052,94 @@ static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
|
|
|
}
|
|
|
}
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
|
|
|
+ struct i2c_msg *msg)
|
|
|
+{
|
|
|
+ u32 val;
|
|
|
+ int idx, pos = 0, ret = 0, total;
|
|
|
+
|
|
|
+ total = qup_i2c_get_data_len(qup);
|
|
|
+
|
|
|
+ /* 2 extra bytes for read tags */
|
|
|
+ while (pos < (total + 2)) {
|
|
|
+ /* Check that FIFO have data */
|
|
|
+ ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
|
|
|
+ SET_BIT, 4 * ONE_BYTE);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(qup->dev, "timeout for fifo not empty");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ val = readl(qup->base + QUP_IN_FIFO_BASE);
|
|
|
+
|
|
|
+ for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
|
|
|
+ /* first 2 bytes are tag bytes */
|
|
|
+ if (pos < 2)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ if (pos >= (total + 2))
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ msg->buf[qup->pos++] = val & 0xff;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+out:
|
|
|
+ qup->blk.data_len -= total;
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
+{
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ qup->msg = msg;
|
|
|
+ qup->pos = 0;
|
|
|
+ enable_irq(qup->irq);
|
|
|
+ qup_i2c_set_blk_data(qup, msg);
|
|
|
+ qup_i2c_set_read_mode_v2(qup, msg->len);
|
|
|
+
|
|
|
+ ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
|
|
|
+
|
|
|
+ do {
|
|
|
+ ret = qup_i2c_issue_xfer_v2(qup, msg);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ ret = qup_i2c_wait_for_complete(qup, msg);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ ret = qup_i2c_read_fifo_v2(qup, msg);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ qup->blk.pos++;
|
|
|
+ } while (qup->blk.pos < qup->blk.count);
|
|
|
+
|
|
|
+err:
|
|
|
+ disable_irq(qup->irq);
|
|
|
+ qup->msg = NULL;
|
|
|
+
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
{
|
|
|
- unsigned long left;
|
|
|
int ret;
|
|
|
|
|
|
qup->msg = msg;
|
|
|
qup->pos = 0;
|
|
|
|
|
|
enable_irq(qup->irq);
|
|
|
-
|
|
|
qup_i2c_set_read_mode(qup, msg->len);
|
|
|
|
|
|
ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
|
|
@@ -436,21 +1159,13 @@ static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
|
|
|
goto err;
|
|
|
|
|
|
do {
|
|
|
- left = wait_for_completion_timeout(&qup->xfer, HZ);
|
|
|
- if (!left) {
|
|
|
- writel(1, qup->base + QUP_SW_RESET);
|
|
|
- ret = -ETIMEDOUT;
|
|
|
+ ret = qup_i2c_wait_for_complete(qup, msg);
|
|
|
+ if (ret)
|
|
|
goto err;
|
|
|
- }
|
|
|
|
|
|
- if (qup->bus_err || qup->qup_err) {
|
|
|
- if (qup->bus_err & QUP_I2C_NACK_FLAG)
|
|
|
- dev_err(qup->dev, "NACK from %x\n", msg->addr);
|
|
|
- ret = -EIO;
|
|
|
+ ret = qup_i2c_read_fifo(qup, msg);
|
|
|
+ if (ret)
|
|
|
goto err;
|
|
|
- }
|
|
|
-
|
|
|
- qup_i2c_read_fifo(qup, msg);
|
|
|
} while (qup->pos < msg->len);
|
|
|
|
|
|
err:
|
|
|
@@ -513,6 +1228,87 @@ static int qup_i2c_xfer(struct i2c_adapter *adap,
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
+static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
|
|
|
+ struct i2c_msg msgs[],
|
|
|
+ int num)
|
|
|
+{
|
|
|
+ struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
|
|
|
+ int ret, len, idx = 0, use_dma = 0;
|
|
|
+
|
|
|
+ ret = pm_runtime_get_sync(qup->dev);
|
|
|
+ if (ret < 0)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ writel(1, qup->base + QUP_SW_RESET);
|
|
|
+ ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
|
|
|
+ if (ret)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ /* Configure QUP as I2C mini core */
|
|
|
+ writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
|
|
|
+ writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
|
|
|
+
|
|
|
+ if ((qup->is_dma)) {
|
|
|
+ /* All i2c_msgs should be transferred using either dma or cpu */
|
|
|
+ for (idx = 0; idx < num; idx++) {
|
|
|
+ if (msgs[idx].len == 0) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ len = (msgs[idx].len > qup->out_fifo_sz) ||
|
|
|
+ (msgs[idx].len > qup->in_fifo_sz);
|
|
|
+
|
|
|
+ if ((!is_vmalloc_addr(msgs[idx].buf)) && len) {
|
|
|
+ use_dma = 1;
|
|
|
+ } else {
|
|
|
+ use_dma = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ do {
|
|
|
+ if (msgs[idx].len == 0) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (qup_i2c_poll_state_i2c_master(qup)) {
|
|
|
+ ret = -EIO;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ qup->is_last = (idx == (num - 1));
|
|
|
+ if (idx)
|
|
|
+ qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
|
|
|
+ else
|
|
|
+ qup->config_run = 0;
|
|
|
+
|
|
|
+ reinit_completion(&qup->xfer);
|
|
|
+
|
|
|
+ if (use_dma) {
|
|
|
+ ret = qup_i2c_bam_xfer(adap, &msgs[idx], num);
|
|
|
+ } else {
|
|
|
+ if (msgs[idx].flags & I2C_M_RD)
|
|
|
+ ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
|
|
|
+ else
|
|
|
+ ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
|
|
|
+ }
|
|
|
+ } while ((idx++ < (num - 1)) && !use_dma && !ret);
|
|
|
+
|
|
|
+ if (!ret)
|
|
|
+ ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
|
|
|
+
|
|
|
+ if (ret == 0)
|
|
|
+ ret = num;
|
|
|
+out:
|
|
|
+ pm_runtime_mark_last_busy(qup->dev);
|
|
|
+ pm_runtime_put_autosuspend(qup->dev);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
static u32 qup_i2c_func(struct i2c_adapter *adap)
|
|
|
{
|
|
|
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
|
|
@@ -523,6 +1319,11 @@ static const struct i2c_algorithm qup_i2c_algo = {
|
|
|
.functionality = qup_i2c_func,
|
|
|
};
|
|
|
|
|
|
+static const struct i2c_algorithm qup_i2c_algo_v2 = {
|
|
|
+ .master_xfer = qup_i2c_xfer_v2,
|
|
|
+ .functionality = qup_i2c_func,
|
|
|
+};
|
|
|
+
|
|
|
/*
|
|
|
* The QUP block will issue a NACK and STOP on the bus when reaching
|
|
|
* the end of the read, the length of the read is specified as one byte
|
|
|
@@ -561,6 +1362,7 @@ static int qup_i2c_probe(struct platform_device *pdev)
|
|
|
int ret, fs_div, hs_div;
|
|
|
int src_clk_freq;
|
|
|
u32 clk_freq = 100000;
|
|
|
+ int blocks;
|
|
|
|
|
|
qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
|
|
|
if (!qup)
|
|
|
@@ -572,6 +1374,68 @@ static int qup_i2c_probe(struct platform_device *pdev)
|
|
|
|
|
|
of_property_read_u32(node, "clock-frequency", &clk_freq);
|
|
|
|
|
|
+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
|
|
|
+ qup->adap.algo = &qup_i2c_algo;
|
|
|
+ qup->adap.quirks = &qup_i2c_quirks;
|
|
|
+ } else {
|
|
|
+ qup->adap.algo = &qup_i2c_algo_v2;
|
|
|
+ ret = qup_i2c_req_dma(qup);
|
|
|
+
|
|
|
+ if (ret == -EPROBE_DEFER)
|
|
|
+ goto fail_dma;
|
|
|
+ else if (ret != 0)
|
|
|
+ goto nodma;
|
|
|
+
|
|
|
+ blocks = (MX_BLOCKS << 1) + 1;
|
|
|
+ qup->btx.sg = devm_kzalloc(&pdev->dev,
|
|
|
+ sizeof(*qup->btx.sg) * blocks,
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!qup->btx.sg) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto fail_dma;
|
|
|
+ }
|
|
|
+ sg_init_table(qup->btx.sg, blocks);
|
|
|
+
|
|
|
+ qup->brx.sg = devm_kzalloc(&pdev->dev,
|
|
|
+ sizeof(*qup->brx.sg) * blocks,
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!qup->brx.sg) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto fail_dma;
|
|
|
+ }
|
|
|
+ sg_init_table(qup->brx.sg, blocks);
|
|
|
+
|
|
|
+ /* 2 tag bytes for each block + 5 for start, stop tags */
|
|
|
+ size = blocks * 2 + 5;
|
|
|
+ qup->dpool = dma_pool_create("qup_i2c-dma-pool", &pdev->dev,
|
|
|
+ size, 4, 0);
|
|
|
+
|
|
|
+ qup->start_tag.start = dma_pool_alloc(qup->dpool, GFP_KERNEL,
|
|
|
+ &qup->start_tag.addr);
|
|
|
+ if (!qup->start_tag.start) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto fail_dma;
|
|
|
+ }
|
|
|
+
|
|
|
+ qup->brx.tag.start = dma_pool_alloc(qup->dpool,
|
|
|
+ GFP_KERNEL,
|
|
|
+ &qup->brx.tag.addr);
|
|
|
+ if (!qup->brx.tag.start) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto fail_dma;
|
|
|
+ }
|
|
|
+
|
|
|
+ qup->btx.tag.start = dma_pool_alloc(qup->dpool,
|
|
|
+ GFP_KERNEL,
|
|
|
+ &qup->btx.tag.addr);
|
|
|
+ if (!qup->btx.tag.start) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto fail_dma;
|
|
|
+ }
|
|
|
+ qup->is_dma = true;
|
|
|
+ }
|
|
|
+
|
|
|
+nodma:
|
|
|
/* We support frequencies up to FAST Mode (400KHz) */
|
|
|
if (!clk_freq || clk_freq > 400000) {
|
|
|
dev_err(qup->dev, "clock frequency not supported %d\n",
|
|
|
@@ -667,10 +1531,10 @@ static int qup_i2c_probe(struct platform_device *pdev)
|
|
|
qup->out_blk_sz, qup->out_fifo_sz);
|
|
|
|
|
|
i2c_set_adapdata(&qup->adap, qup);
|
|
|
- qup->adap.algo = &qup_i2c_algo;
|
|
|
- qup->adap.quirks = &qup_i2c_quirks;
|
|
|
qup->adap.dev.parent = qup->dev;
|
|
|
qup->adap.dev.of_node = pdev->dev.of_node;
|
|
|
+ qup->is_last = true;
|
|
|
+
|
|
|
strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
|
|
|
|
|
|
pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
|
|
|
@@ -689,6 +1553,11 @@ static int qup_i2c_probe(struct platform_device *pdev)
|
|
|
pm_runtime_set_suspended(qup->dev);
|
|
|
fail:
|
|
|
qup_i2c_disable_clocks(qup);
|
|
|
+fail_dma:
|
|
|
+ if (qup->btx.dma)
|
|
|
+ dma_release_channel(qup->btx.dma);
|
|
|
+ if (qup->brx.dma)
|
|
|
+ dma_release_channel(qup->brx.dma);
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
@@ -696,6 +1565,18 @@ static int qup_i2c_remove(struct platform_device *pdev)
|
|
|
{
|
|
|
struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
|
|
|
|
|
|
+ if (qup->is_dma) {
|
|
|
+ dma_pool_free(qup->dpool, qup->start_tag.start,
|
|
|
+ qup->start_tag.addr);
|
|
|
+ dma_pool_free(qup->dpool, qup->brx.tag.start,
|
|
|
+ qup->brx.tag.addr);
|
|
|
+ dma_pool_free(qup->dpool, qup->btx.tag.start,
|
|
|
+ qup->btx.tag.addr);
|
|
|
+ dma_pool_destroy(qup->dpool);
|
|
|
+ dma_release_channel(qup->btx.dma);
|
|
|
+ dma_release_channel(qup->brx.dma);
|
|
|
+ }
|
|
|
+
|
|
|
disable_irq(qup->irq);
|
|
|
qup_i2c_disable_clocks(qup);
|
|
|
i2c_del_adapter(&qup->adap);
|
Linus Torvalds