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@@ -788,31 +788,37 @@ err_exit:
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return err;
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}
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-static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self,
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- bool itr_enabled)
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+static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
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{
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unsigned int i = 0U;
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+ u32 itr_tx = 2U;
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+ u32 itr_rx = 2U;
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- if (itr_enabled && self->aq_nic_cfg->itr) {
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+ switch (self->aq_nic_cfg->itr) {
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+ case AQ_CFG_INTERRUPT_MODERATION_ON:
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+ case AQ_CFG_INTERRUPT_MODERATION_AUTO:
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tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
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tdm_tdm_intr_moder_en_set(self, 1U);
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rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
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rdm_rdm_intr_moder_en_set(self, 1U);
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- PHAL_ATLANTIC_B0->itr_tx = 2U;
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- PHAL_ATLANTIC_B0->itr_rx = 2U;
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+ if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
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+ /* HW timers are in 2us units */
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+ int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
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+ int tx_min_timer = tx_max_timer / 2;
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- if (self->aq_nic_cfg->itr != 0xFFFFU) {
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- unsigned int max_timer = self->aq_nic_cfg->itr / 2U;
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- unsigned int min_timer = self->aq_nic_cfg->itr / 32U;
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+ int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
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+ int rx_min_timer = rx_max_timer / 2;
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- max_timer = min(0x1FFU, max_timer);
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- min_timer = min(0xFFU, min_timer);
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+ tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
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+ tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
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+ rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
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+ rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
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- PHAL_ATLANTIC_B0->itr_tx |= min_timer << 0x8U;
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- PHAL_ATLANTIC_B0->itr_tx |= max_timer << 0x10U;
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- PHAL_ATLANTIC_B0->itr_rx |= min_timer << 0x8U;
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- PHAL_ATLANTIC_B0->itr_rx |= max_timer << 0x10U;
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+ itr_tx |= tx_min_timer << 0x8U;
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+ itr_tx |= tx_max_timer << 0x10U;
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+ itr_rx |= rx_min_timer << 0x8U;
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+ itr_rx |= rx_max_timer << 0x10U;
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} else {
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static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
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{0xffU, 0xffU}, /* 10Gbit */
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@@ -836,34 +842,36 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self,
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hw_atl_utils_mbps_2_speed_index(
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self->aq_link_status.mbps);
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- PHAL_ATLANTIC_B0->itr_tx |=
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- hw_atl_b0_timers_table_tx_[speed_index]
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- [0] << 0x8U; /* set min timer value */
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- PHAL_ATLANTIC_B0->itr_tx |=
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- hw_atl_b0_timers_table_tx_[speed_index]
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- [1] << 0x10U; /* set max timer value */
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-
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- PHAL_ATLANTIC_B0->itr_rx |=
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- hw_atl_b0_timers_table_rx_[speed_index]
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- [0] << 0x8U; /* set min timer value */
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- PHAL_ATLANTIC_B0->itr_rx |=
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- hw_atl_b0_timers_table_rx_[speed_index]
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- [1] << 0x10U; /* set max timer value */
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+ /* Update user visible ITR settings */
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+ self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
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+ [speed_index][1] * 2;
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+ self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
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+ [speed_index][1] * 2;
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+
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+ itr_tx |= hw_atl_b0_timers_table_tx_
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+ [speed_index][0] << 0x8U;
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+ itr_tx |= hw_atl_b0_timers_table_tx_
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+ [speed_index][1] << 0x10U;
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+
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+ itr_rx |= hw_atl_b0_timers_table_rx_
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+ [speed_index][0] << 0x8U;
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+ itr_rx |= hw_atl_b0_timers_table_rx_
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+ [speed_index][1] << 0x10U;
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}
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- } else {
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+ break;
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+ case AQ_CFG_INTERRUPT_MODERATION_OFF:
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tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
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tdm_tdm_intr_moder_en_set(self, 0U);
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rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
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rdm_rdm_intr_moder_en_set(self, 0U);
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- PHAL_ATLANTIC_B0->itr_tx = 0U;
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- PHAL_ATLANTIC_B0->itr_rx = 0U;
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+ itr_tx = 0U;
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+ itr_rx = 0U;
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+ break;
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}
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for (i = HW_ATL_B0_RINGS_MAX; i--;) {
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- reg_tx_intr_moder_ctrl_set(self,
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- PHAL_ATLANTIC_B0->itr_tx, i);
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- reg_rx_intr_moder_ctrl_set(self,
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- PHAL_ATLANTIC_B0->itr_rx, i);
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+ reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
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+ reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
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}
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return aq_hw_err_from_flags(self);
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