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@@ -167,9 +167,11 @@ int hwmgr_early_init(struct pp_instance *handle)
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hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
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PP_ENABLE_GFX_CG_THRU_SMU);
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hwmgr->pp_table_version = PP_TABLE_V0;
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+ hwmgr->od_enabled = false;
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smu7_init_function_pointers(hwmgr);
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break;
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case AMDGPU_FAMILY_CZ:
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+ hwmgr->od_enabled = false;
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hwmgr->smumgr_funcs = &cz_smu_funcs;
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cz_init_function_pointers(hwmgr);
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break;
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@@ -181,6 +183,7 @@ int hwmgr_early_init(struct pp_instance *handle)
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hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
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PP_ENABLE_GFX_CG_THRU_SMU);
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hwmgr->pp_table_version = PP_TABLE_V0;
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+ hwmgr->od_enabled = false;
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break;
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case CHIP_TONGA:
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hwmgr->smumgr_funcs = &tonga_smu_funcs;
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@@ -218,6 +221,7 @@ int hwmgr_early_init(struct pp_instance *handle)
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case AMDGPU_FAMILY_RV:
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switch (hwmgr->chip_id) {
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case CHIP_RAVEN:
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+ hwmgr->od_enabled = false;
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hwmgr->smumgr_funcs = &rv_smu_funcs;
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rv_init_function_pointers(hwmgr);
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break;
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