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@@ -156,15 +156,18 @@ static int __init pit_clockevent_init(unsigned long rate, int irq)
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return 0;
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}
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-static void __init pit_timer_init(struct device_node *np)
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+static int __init pit_timer_init(struct device_node *np)
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{
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struct clk *pit_clk;
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void __iomem *timer_base;
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unsigned long clk_rate;
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- int irq;
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+ int irq, ret;
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timer_base = of_iomap(np, 0);
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- BUG_ON(!timer_base);
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+ if (!timer_base) {
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+ pr_err("Failed to iomap");
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+ return -ENXIO;
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+ }
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/*
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* PIT0 and PIT1 can be chained to build a 64-bit timer,
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@@ -175,12 +178,16 @@ static void __init pit_timer_init(struct device_node *np)
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clkevt_base = timer_base + PITn_OFFSET(3);
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irq = irq_of_parse_and_map(np, 0);
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- BUG_ON(irq <= 0);
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+ if (irq <= 0)
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+ return -EINVAL;
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pit_clk = of_clk_get(np, 0);
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- BUG_ON(IS_ERR(pit_clk));
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+ if (IS_ERR(pit_clk))
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+ return PTR_ERR(pit_clk);
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- BUG_ON(clk_prepare_enable(pit_clk));
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+ ret = clk_prepare_enable(pit_clk);
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+ if (ret)
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+ return ret;
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clk_rate = clk_get_rate(pit_clk);
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cycle_per_jiffy = clk_rate / (HZ);
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@@ -188,8 +195,10 @@ static void __init pit_timer_init(struct device_node *np)
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/* enable the pit module */
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__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
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- BUG_ON(pit_clocksource_init(clk_rate));
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+ ret = pit_clocksource_init(clk_rate);
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+ if (ret)
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+ return ret;
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- pit_clockevent_init(clk_rate, irq);
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+ return pit_clockevent_init(clk_rate, irq);
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}
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-CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
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+CLOCKSOURCE_OF_DECLARE_RET(vf610, "fsl,vf610-pit", pit_timer_init);
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