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+===================================
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+refcount_t API compared to atomic_t
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+===================================
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+
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+.. contents:: :local:
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+
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+Introduction
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+============
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+
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+The goal of refcount_t API is to provide a minimal API for implementing
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+an object's reference counters. While a generic architecture-independent
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+implementation from lib/refcount.c uses atomic operations underneath,
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+there are a number of differences between some of the ``refcount_*()`` and
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+``atomic_*()`` functions with regards to the memory ordering guarantees.
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+This document outlines the differences and provides respective examples
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+in order to help maintainers validate their code against the change in
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+these memory ordering guarantees.
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+
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+The terms used through this document try to follow the formal LKMM defined in
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+github.com/aparri/memory-model/blob/master/Documentation/explanation.txt
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+
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+memory-barriers.txt and atomic_t.txt provide more background to the
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+memory ordering in general and for atomic operations specifically.
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+
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+Relevant types of memory ordering
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+=================================
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+
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+.. note:: The following section only covers some of the memory
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+ ordering types that are relevant for the atomics and reference
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+ counters and used through this document. For a much broader picture
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+ please consult memory-barriers.txt document.
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+
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+In the absence of any memory ordering guarantees (i.e. fully unordered)
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+atomics & refcounters only provide atomicity and
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+program order (po) relation (on the same CPU). It guarantees that
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+each ``atomic_*()`` and ``refcount_*()`` operation is atomic and instructions
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+are executed in program order on a single CPU.
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+This is implemented using :c:func:`READ_ONCE`/:c:func:`WRITE_ONCE` and
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+compare-and-swap primitives.
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+
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+A strong (full) memory ordering guarantees that all prior loads and
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+stores (all po-earlier instructions) on the same CPU are completed
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+before any po-later instruction is executed on the same CPU.
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+It also guarantees that all po-earlier stores on the same CPU
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+and all propagated stores from other CPUs must propagate to all
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+other CPUs before any po-later instruction is executed on the original
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+CPU (A-cumulative property). This is implemented using :c:func:`smp_mb`.
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+
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+A RELEASE memory ordering guarantees that all prior loads and
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+stores (all po-earlier instructions) on the same CPU are completed
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+before the operation. It also guarantees that all po-earlier
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+stores on the same CPU and all propagated stores from other CPUs
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+must propagate to all other CPUs before the release operation
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+(A-cumulative property). This is implemented using
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+:c:func:`smp_store_release`.
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+
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+A control dependency (on success) for refcounters guarantees that
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+if a reference for an object was successfully obtained (reference
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+counter increment or addition happened, function returned true),
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+then further stores are ordered against this operation.
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+Control dependency on stores are not implemented using any explicit
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+barriers, but rely on CPU not to speculate on stores. This is only
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+a single CPU relation and provides no guarantees for other CPUs.
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+
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+
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+Comparison of functions
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+=======================
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+
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+case 1) - non-"Read/Modify/Write" (RMW) ops
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+-------------------------------------------
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+
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+Function changes:
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+
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+ * :c:func:`atomic_set` --> :c:func:`refcount_set`
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+ * :c:func:`atomic_read` --> :c:func:`refcount_read`
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+
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+Memory ordering guarantee changes:
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+
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+ * none (both fully unordered)
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+
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+
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+case 2) - increment-based ops that return no value
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+--------------------------------------------------
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+
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+Function changes:
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+
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+ * :c:func:`atomic_inc` --> :c:func:`refcount_inc`
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+ * :c:func:`atomic_add` --> :c:func:`refcount_add`
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+
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+Memory ordering guarantee changes:
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+
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+ * none (both fully unordered)
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+
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+case 3) - decrement-based RMW ops that return no value
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+------------------------------------------------------
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+
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+Function changes:
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+
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+ * :c:func:`atomic_dec` --> :c:func:`refcount_dec`
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+
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+Memory ordering guarantee changes:
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+
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+ * fully unordered --> RELEASE ordering
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+
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+
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+case 4) - increment-based RMW ops that return a value
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+-----------------------------------------------------
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+
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+Function changes:
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+
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+ * :c:func:`atomic_inc_not_zero` --> :c:func:`refcount_inc_not_zero`
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+ * no atomic counterpart --> :c:func:`refcount_add_not_zero`
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+
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+Memory ordering guarantees changes:
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+
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+ * fully ordered --> control dependency on success for stores
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+
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+.. note:: We really assume here that necessary ordering is provided as a
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+ result of obtaining pointer to the object!
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+
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+
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+case 5) - decrement-based RMW ops that return a value
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+-----------------------------------------------------
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+
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+Function changes:
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+
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+ * :c:func:`atomic_dec_and_test` --> :c:func:`refcount_dec_and_test`
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+ * :c:func:`atomic_sub_and_test` --> :c:func:`refcount_sub_and_test`
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+ * no atomic counterpart --> :c:func:`refcount_dec_if_one`
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+ * ``atomic_add_unless(&var, -1, 1)`` --> ``refcount_dec_not_one(&var)``
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+
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+Memory ordering guarantees changes:
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+
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+ * fully ordered --> RELEASE ordering + control dependency
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+
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+.. note:: :c:func:`atomic_add_unless` only provides full order on success.
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+
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+
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+case 6) - lock-based RMW
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+------------------------
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+
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+Function changes:
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+
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+ * :c:func:`atomic_dec_and_lock` --> :c:func:`refcount_dec_and_lock`
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+ * :c:func:`atomic_dec_and_mutex_lock` --> :c:func:`refcount_dec_and_mutex_lock`
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+
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+Memory ordering guarantees changes:
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+
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+ * fully ordered --> RELEASE ordering + control dependency + hold
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+ :c:func:`spin_lock` on success
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