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@@ -1259,6 +1259,15 @@ enum radeon_dpm_event_src {
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RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
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};
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+enum radeon_vce_level {
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+ RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
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+ RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
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+ RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
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+ RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
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+ RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
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+ RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
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+};
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+
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struct radeon_ps {
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u32 caps; /* vbios flags */
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u32 class; /* vbios flags */
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@@ -1269,6 +1278,8 @@ struct radeon_ps {
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/* VCE clocks */
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u32 evclk;
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u32 ecclk;
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+ bool vce_active;
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+ enum radeon_vce_level vce_level;
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/* asic priv */
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void *ps_priv;
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};
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@@ -1480,6 +1491,7 @@ struct radeon_dpm {
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/* special states active */
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bool thermal_active;
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bool uvd_active;
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+ bool vce_active;
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/* thermal handling */
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struct radeon_dpm_thermal thermal;
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/* forced levels */
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