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@@ -86,6 +86,8 @@ struct acr_r352_flcn_bl_desc {
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u32 code_entry_point;
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u32 data_dma_base;
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u32 data_size;
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+ u32 code_dma_base1;
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+ u32 data_dma_base1;
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};
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/**
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@@ -107,10 +109,12 @@ acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr,
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desc->ctx_dma = FALCON_DMAIDX_UCODE;
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desc->code_dma_base = lower_32_bits(addr_code);
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+ desc->code_dma_base1 = upper_32_bits(addr_code);
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desc->non_sec_code_off = pdesc->app_resident_code_offset;
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desc->non_sec_code_size = pdesc->app_resident_code_size;
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desc->code_entry_point = pdesc->app_imem_entry;
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desc->data_dma_base = lower_32_bits(addr_data);
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+ desc->data_dma_base1 = upper_32_bits(addr_data);
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desc->data_size = pdesc->app_resident_data_size;
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}
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