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@@ -458,6 +458,11 @@ static int xgpu_vi_request_reset(struct amdgpu_device *adev)
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return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
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return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
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}
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}
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+static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev)
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+{
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+ return xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL);
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+}
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+
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static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
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static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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bool init)
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{
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{
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@@ -613,5 +618,6 @@ const struct amdgpu_virt_ops xgpu_vi_virt_ops = {
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.req_full_gpu = xgpu_vi_request_full_gpu_access,
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.req_full_gpu = xgpu_vi_request_full_gpu_access,
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.rel_full_gpu = xgpu_vi_release_full_gpu_access,
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.rel_full_gpu = xgpu_vi_release_full_gpu_access,
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.reset_gpu = xgpu_vi_request_reset,
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.reset_gpu = xgpu_vi_request_reset,
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+ .wait_reset = xgpu_vi_wait_reset_cmpl,
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.trans_msg = NULL, /* Does not need to trans VF errors to host. */
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.trans_msg = NULL, /* Does not need to trans VF errors to host. */
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};
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};
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