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@@ -75,6 +75,34 @@ enum {
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#define WAIT_TIMEOUT 1000 /* ms */
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#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
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+/**
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+ * struct i2c_spec_values:
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+ * @min_low_ns: min LOW period of the SCL clock
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+ * @min_high_ns: min HIGH period of the SCL cloc
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+ * @min_setup_start_ns: min set-up time for a repeated START conditio
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+ * @max_data_hold_ns: max data hold time
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+ */
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+struct i2c_spec_values {
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+ unsigned long min_low_ns;
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+ unsigned long min_high_ns;
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+ unsigned long min_setup_start_ns;
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+ unsigned long max_data_hold_ns;
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+};
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+
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+static const struct i2c_spec_values standard_mode_spec = {
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+ .min_low_ns = 4700,
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+ .min_high_ns = 4000,
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+ .min_setup_start_ns = 4700,
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+ .max_data_hold_ns = 3450,
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+};
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+
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+static const struct i2c_spec_values fast_mode_spec = {
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+ .min_low_ns = 1300,
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+ .min_high_ns = 600,
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+ .min_setup_start_ns = 600,
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+ .max_data_hold_ns = 900,
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+};
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+
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/**
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* struct rk3x_i2c_calced_timings:
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* @div_low: Divider output for low
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@@ -459,6 +487,21 @@ out:
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return IRQ_HANDLED;
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}
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+/**
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+ * Get timing values of I2C specification
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+ *
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+ * @speed: Desired SCL frequency
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+ *
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+ * Returns: Matched i2c spec values.
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+ */
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+static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
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+{
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+ if (speed <= 100000)
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+ return &standard_mode_spec;
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+ else
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+ return &fast_mode_spec;
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+}
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+
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/**
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* Calculate divider values for desired SCL frequency
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*
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@@ -474,10 +517,6 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate,
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struct i2c_timings *t,
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struct rk3x_i2c_calced_timings *t_calc)
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{
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- unsigned long spec_min_low_ns, spec_min_high_ns;
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- unsigned long spec_setup_start, spec_max_data_hold_ns;
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- unsigned long data_hold_buffer_ns;
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-
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unsigned long min_low_ns, min_high_ns;
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unsigned long max_low_ns, min_total_ns;
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@@ -489,6 +528,8 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate,
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unsigned long min_div_for_hold, min_total_div;
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unsigned long extra_div, extra_low_div, ideal_low_div;
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+ unsigned long data_hold_buffer_ns = 50;
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+ const struct i2c_spec_values *spec;
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int ret = 0;
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/* Only support standard-mode and fast-mode */
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@@ -511,22 +552,8 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate,
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* This is because the i2c host on Rockchip holds the data line
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* for half the low time.
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*/
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- if (t->bus_freq_hz <= 100000) {
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- /* Standard-mode */
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- spec_min_low_ns = 4700;
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- spec_setup_start = 4700;
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- spec_min_high_ns = 4000;
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- spec_max_data_hold_ns = 3450;
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- data_hold_buffer_ns = 50;
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- } else {
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- /* Fast-mode */
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- spec_min_low_ns = 1300;
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- spec_setup_start = 600;
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- spec_min_high_ns = 600;
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- spec_max_data_hold_ns = 900;
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- data_hold_buffer_ns = 50;
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- }
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- min_high_ns = t->scl_rise_ns + spec_min_high_ns;
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+ spec = rk3x_i2c_get_spec(t->bus_freq_hz);
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+ min_high_ns = t->scl_rise_ns + spec->min_high_ns;
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/*
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* Timings for repeated start:
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@@ -536,14 +563,14 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate,
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* We need to account for those rules in picking our "high" time so
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* we meet tSU;STA and tHD;STA times.
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*/
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- min_high_ns = max(min_high_ns,
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- DIV_ROUND_UP((t->scl_rise_ns + spec_setup_start) * 1000, 875));
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- min_high_ns = max(min_high_ns,
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- DIV_ROUND_UP((t->scl_rise_ns + spec_setup_start +
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- t->sda_fall_ns + spec_min_high_ns), 2));
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-
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- min_low_ns = t->scl_fall_ns + spec_min_low_ns;
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- max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns;
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+ min_high_ns = max(min_high_ns, DIV_ROUND_UP(
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+ (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
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+ min_high_ns = max(min_high_ns, DIV_ROUND_UP(
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+ (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
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+ spec->min_high_ns), 2));
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+
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+ min_low_ns = t->scl_fall_ns + spec->min_low_ns;
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+ max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
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min_total_ns = min_low_ns + min_high_ns;
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/* Adjust to avoid overflow */
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