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@@ -892,8 +892,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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ld r6, VCPU_DAWRX(r4)
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ld r7, VCPU_CIABR(r4)
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ld r8, VCPU_TAR(r4)
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+ /*
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+ * Handle broken DAWR case by not writing it. This means we
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+ * can still store the DAWR register for migration.
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+ */
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+BEGIN_FTR_SECTION
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mtspr SPRN_DAWR, r5
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mtspr SPRN_DAWRX, r6
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+END_FTR_SECTION_IFSET(CPU_FTR_DAWR)
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mtspr SPRN_CIABR, r7
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mtspr SPRN_TAR, r8
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ld r5, VCPU_IC(r4)
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@@ -1855,6 +1861,10 @@ BEGIN_FTR_SECTION
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ld r6, STACK_SLOT_DAWR(r1)
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ld r7, STACK_SLOT_DAWRX(r1)
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mtspr SPRN_CIABR, r5
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+ /*
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+ * If the DAWR doesn't work, it's ok to write these here as
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+ * this value should always be zero
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+ */
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mtspr SPRN_DAWR, r6
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mtspr SPRN_DAWRX, r7
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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