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@@ -697,16 +697,16 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
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#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
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#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
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-#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
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-#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
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-#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
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+#define IXGBE_FCBUFF_VALID BIT(0) /* DMA Context Valid */
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+#define IXGBE_FCBUFF_BUFFSIZE (3u << 3) /* User Buffer Size */
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+#define IXGBE_FCBUFF_WRCONTX BIT(7) /* 0: Initiator, 1: Target */
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#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
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#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
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#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
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#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
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#define IXGBE_FCBUFF_OFFSET_SHIFT 16
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-#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
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-#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
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+#define IXGBE_FCDMARW_WE BIT(14) /* Write enable */
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+#define IXGBE_FCDMARW_RE BIT(15) /* Read enable */
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#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
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#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
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#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
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@@ -723,23 +723,23 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
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#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
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#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
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-#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
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-#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
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+#define IXGBE_FCFLT_VALID BIT(0) /* Filter Context Valid */
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+#define IXGBE_FCFLT_FIRST BIT(1) /* Filter First */
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#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
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#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
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-#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
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-#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
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-#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
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+#define IXGBE_FCFLTRW_RVALDT BIT(13) /* Fast Re-Validation */
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+#define IXGBE_FCFLTRW_WE BIT(14) /* Write Enable */
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+#define IXGBE_FCFLTRW_RE BIT(15) /* Read Enable */
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/* FCoE Receive Control */
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#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
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-#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
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-#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
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-#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
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-#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
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-#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
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-#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
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-#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
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-#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
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+#define IXGBE_FCRXCTRL_FCOELLI BIT(0) /* Low latency interrupt */
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+#define IXGBE_FCRXCTRL_SAVBAD BIT(1) /* Save Bad Frames */
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+#define IXGBE_FCRXCTRL_FRSTRDH BIT(2) /* EN 1st Read Header */
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+#define IXGBE_FCRXCTRL_LASTSEQH BIT(3) /* EN Last Header in Seq */
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+#define IXGBE_FCRXCTRL_ALLH BIT(4) /* EN All Headers */
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+#define IXGBE_FCRXCTRL_FRSTSEQH BIT(5) /* EN 1st Seq. Header */
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+#define IXGBE_FCRXCTRL_ICRC BIT(6) /* Ignore Bad FC CRC */
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+#define IXGBE_FCRXCTRL_FCCRCBO BIT(7) /* FC CRC Byte Ordering */
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#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
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#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
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/* FCoE Redirection */
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@@ -1256,20 +1256,20 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
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#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
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#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
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-#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
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-#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
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-#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
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-#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
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-#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
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-#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
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+#define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
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+#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
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+#define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
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+#define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
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+#define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */
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+#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */
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#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
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#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
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#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
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-#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
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-#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
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-#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
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-#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
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+#define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
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+#define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
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+#define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */
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+#define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
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#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
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/* MSCA Bit Masks */
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@@ -1748,7 +1748,7 @@ enum {
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#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */
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#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
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#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
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-#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
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+#define IXGBE_ETQF_POOL_ENABLE BIT(26) /* bit 26 */
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#define IXGBE_ETQF_POOL_SHIFT 20
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#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
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@@ -1874,20 +1874,20 @@ enum {
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#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
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#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
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#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
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-#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_10G_XAUI (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_10G_KX4 (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_10G_CX4 (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_1G_BX (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_1G_KX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_1G_SFI (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC_1G_KX_BX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
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#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
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#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
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#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
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-#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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-#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC2_10G_KR (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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+#define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
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#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
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@@ -2840,15 +2840,15 @@ struct ixgbe_adv_tx_context_desc {
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#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
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#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
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#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
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-#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
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-#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
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-#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
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-#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
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-#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
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-#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
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-#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
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-#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
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-#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
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+#define IXGBE_ADVTXD_FCOEF_SOF (BIT(2) << 10) /* FC SOF index */
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+#define IXGBE_ADVTXD_FCOEF_PARINC (BIT(3) << 10) /* Rel_Off in F_CTL */
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+#define IXGBE_ADVTXD_FCOEF_ORIE (BIT(4) << 10) /* Orientation: End */
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+#define IXGBE_ADVTXD_FCOEF_ORIS (BIT(5) << 10) /* Orientation: Start */
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+#define IXGBE_ADVTXD_FCOEF_EOF_N (0u << 10) /* 00: EOFn */
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+#define IXGBE_ADVTXD_FCOEF_EOF_T (1u << 10) /* 01: EOFt */
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+#define IXGBE_ADVTXD_FCOEF_EOF_NI (2u << 10) /* 10: EOFni */
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+#define IXGBE_ADVTXD_FCOEF_EOF_A (3u << 10) /* 11: EOFa */
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+#define IXGBE_ADVTXD_FCOEF_EOF_MASK (3u << 10) /* FC EOF index */
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#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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@@ -3583,7 +3583,7 @@ struct ixgbe_info {
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#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
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#define IXGBE_FUSES0_300MHZ BIT(5)
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-#define IXGBE_FUSES0_REV_MASK (3 << 6)
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+#define IXGBE_FUSES0_REV_MASK (3u << 6)
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#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
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#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
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@@ -3597,25 +3597,25 @@ struct ixgbe_info {
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#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
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#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
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-#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
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-#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
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+#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B BIT(9)
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+#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS BIT(11)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (7u << 8)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2u << 8)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4u << 8)
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#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12)
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#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
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-#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
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-
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-#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
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-#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ BIT(14)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC BIT(15)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX BIT(16)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR BIT(18)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX BIT(24)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR BIT(26)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE BIT(29)
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+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART BIT(31)
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+
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+#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE BIT(28)
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+#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE BIT(29)
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#define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0)
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#define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1)
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@@ -3623,28 +3623,28 @@ struct ixgbe_info {
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#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12)
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#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19)
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-#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
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-#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
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-#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
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+#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN BIT(6)
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+#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN BIT(15)
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+#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN BIT(16)
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-#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
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-#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
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+#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL BIT(4)
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+#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS BIT(2)
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-#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
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+#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (3u << 16)
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-#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
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-#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
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-#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
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-#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
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+#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN BIT(1)
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+#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN BIT(2)
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+#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3)
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+#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31)
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#define IXGBE_KX4_LINK_CNTL_1 0x4C
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX (1 << 16)
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 (1 << 17)
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX (1 << 24)
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 (1 << 25)
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE (1 << 29)
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP (1 << 30)
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-#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART (1 << 31)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX BIT(16)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 BIT(17)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX BIT(24)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 BIT(25)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE BIT(29)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP BIT(30)
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+#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART BIT(31)
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#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
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#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
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@@ -3660,7 +3660,7 @@ struct ixgbe_info {
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#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
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#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
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#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
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-#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
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+#define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
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#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
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#define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1
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#define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2
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Jacob Keller