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@@ -87,6 +87,13 @@ mb_incoherent(void)
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#define __smp_mb__after_atomic() __smp_mb()
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#define __smp_mb__after_atomic() __smp_mb()
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#endif
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#endif
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+/*
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+ * The TILE architecture does not do speculative reads; this ensures
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+ * that a control dependency also orders against loads and already provides
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+ * a LOAD->{LOAD,STORE} order and can forgo the additional RMB.
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+ */
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+#define smp_acquire__after_ctrl_dep() barrier()
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+
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#include <asm-generic/barrier.h>
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#include <asm-generic/barrier.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASSEMBLY__ */
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