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@@ -27,7 +27,7 @@
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/*
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/*
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* MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
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* MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
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- * Since IRQ block starts from address 0x002 we need to substract that from
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+ * Since IRQ block starts from address 0x002 we need to subtract that from
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* the actual IRQ status register address.
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* the actual IRQ status register address.
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*/
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*/
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#define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
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#define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
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