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@@ -613,7 +613,6 @@ struct fw_ofld_tx_data_wr {
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struct fw_cmd_wr {
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__be32 op_dma;
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-#define FW_CMD_WR_DMA (1U << 17)
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__be32 len16_pkd;
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__be64 cookie_daddr;
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};
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@@ -2644,11 +2643,6 @@ struct fw_port_stats_cmd {
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} u;
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};
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-#define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
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-#define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
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-#define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
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-#define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
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-
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/* port loopback stats */
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#define FW_NUM_LB_STATS 16
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enum fw_port_lb_stats_index {
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@@ -2704,22 +2698,13 @@ struct fw_port_lb_stats_cmd {
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} u;
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};
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-#define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
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-#define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
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-#define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
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-#define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
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-
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struct fw_rss_ind_tbl_cmd {
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__be32 op_to_viid;
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-#define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
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__be32 retval_len16;
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__be16 niqid;
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__be16 startidx;
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__be32 r3;
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__be32 iq0_to_iq2;
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-#define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
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-#define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
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-#define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
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__be32 iq3_to_iq5;
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__be32 iq6_to_iq8;
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__be32 iq9_to_iq11;
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@@ -2733,6 +2718,18 @@ struct fw_rss_ind_tbl_cmd {
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__be32 r15_lo;
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};
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+#define FW_RSS_IND_TBL_CMD_VIID_S 0
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+#define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
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+
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+#define FW_RSS_IND_TBL_CMD_IQ0_S 20
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+#define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
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+
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+#define FW_RSS_IND_TBL_CMD_IQ1_S 10
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+#define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
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+
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+#define FW_RSS_IND_TBL_CMD_IQ2_S 0
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+#define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
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+
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struct fw_rss_glb_config_cmd {
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__be32 op_to_write;
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__be32 retval_len16;
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@@ -2746,27 +2743,75 @@ struct fw_rss_glb_config_cmd {
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struct fw_rss_glb_config_basicvirtual {
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__be32 mode_pkd;
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__be32 synmapen_to_hashtoeplitz;
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-#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
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-#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
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-#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
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-#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
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-#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
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-#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
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-#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
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-#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
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-#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
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__be64 r8;
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__be64 r9;
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} basicvirtual;
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} u;
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};
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-#define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
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-#define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
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+#define FW_RSS_GLB_CONFIG_CMD_MODE_S 28
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+#define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf
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+#define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
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+#define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
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+ (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
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#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
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#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
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+#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8
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+#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
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+#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \
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+ FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7
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+#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
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+#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \
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+ FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6
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+#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
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+#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \
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+ FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5
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+#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
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+#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \
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+ FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4
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+#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
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+#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \
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+ FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3
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+#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
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+#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \
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+ FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2
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+#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
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+#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \
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+ FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1
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+#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
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+#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \
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+ FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
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+
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+#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0
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+#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
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+ ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
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+#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \
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+ FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
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+
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struct fw_rss_vi_config_cmd {
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__be32 op_to_viid;
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#define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
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@@ -2780,19 +2825,51 @@ struct fw_rss_vi_config_cmd {
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struct fw_rss_vi_config_basicvirtual {
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__be32 r6;
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__be32 defaultq_to_udpen;
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-#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
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-#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
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-#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
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-#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
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-#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
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-#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
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-#define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
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__be64 r9;
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__be64 r10;
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} basicvirtual;
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} u;
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};
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+#define FW_RSS_VI_CONFIG_CMD_VIID_S 0
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+#define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
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+
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+#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16
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+#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff
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+#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \
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+ ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
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+#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \
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+ (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
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+ FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
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+
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+#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4
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+#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \
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+ ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
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+#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \
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+ FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
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+
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+#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3
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+#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \
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+ ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
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+#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \
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+ FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
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+
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+#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2
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+#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \
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+ ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
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+#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \
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+ FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
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+
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+#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1
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+#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \
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+ ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
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+#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \
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+ FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
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+
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+#define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0
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+#define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
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+#define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
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+
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struct fw_clip_cmd {
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__be32 op_to_write;
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__be32 alloc_to_len16;
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@@ -2801,19 +2878,13 @@ struct fw_clip_cmd {
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__be32 r4[2];
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};
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-#define S_FW_CLIP_CMD_ALLOC 31
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-#define M_FW_CLIP_CMD_ALLOC 0x1
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-#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
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-#define G_FW_CLIP_CMD_ALLOC(x) \
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- (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
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-#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
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+#define FW_CLIP_CMD_ALLOC_S 31
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+#define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)
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+#define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U)
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-#define S_FW_CLIP_CMD_FREE 30
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-#define M_FW_CLIP_CMD_FREE 0x1
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-#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
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-#define G_FW_CLIP_CMD_FREE(x) \
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- (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
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-#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
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+#define FW_CLIP_CMD_FREE_S 30
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+#define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)
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+#define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U)
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enum fw_error_type {
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FW_ERROR_TYPE_EXCEPTION = 0x0,
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@@ -2852,7 +2923,6 @@ struct fw_error_cmd {
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struct fw_debug_cmd {
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__be32 op_type;
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-#define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
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__be32 len16_pkd;
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union fw_debug {
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struct fw_debug_assert {
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@@ -2875,19 +2945,35 @@ struct fw_debug_cmd {
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} u;
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};
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-#define FW_PCIE_FW_ERR (1U << 31)
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-#define FW_PCIE_FW_INIT (1U << 30)
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-#define FW_PCIE_FW_HALT (1U << 29)
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-#define FW_PCIE_FW_MASTER_VLD (1U << 15)
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-#define FW_PCIE_FW_MASTER_MASK 0x7
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-#define FW_PCIE_FW_MASTER_SHIFT 12
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-#define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT)
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-#define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
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- FW_PCIE_FW_MASTER_MASK)
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-#define FW_PCIE_FW_EVAL_MASK 0x7
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-#define FW_PCIE_FW_EVAL_SHIFT 24
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-#define FW_PCIE_FW_EVAL_GET(x) (((x) >> FW_PCIE_FW_EVAL_SHIFT) & \
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- FW_PCIE_FW_EVAL_MASK)
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+#define FW_DEBUG_CMD_TYPE_S 0
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+#define FW_DEBUG_CMD_TYPE_M 0xff
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+#define FW_DEBUG_CMD_TYPE_G(x) \
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+ (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
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+
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+#define PCIE_FW_ERR_S 31
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+#define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
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+#define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
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+
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+#define PCIE_FW_INIT_S 30
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+#define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)
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+#define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U)
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+
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+#define PCIE_FW_HALT_S 29
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+#define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)
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+#define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U)
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+
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+#define PCIE_FW_EVAL_S 24
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+#define PCIE_FW_EVAL_M 0x7
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+#define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
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+
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+#define PCIE_FW_MASTER_VLD_S 15
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+#define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
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+#define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U)
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+
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+#define PCIE_FW_MASTER_S 12
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+#define PCIE_FW_MASTER_M 0x7
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+#define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)
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+#define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
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struct fw_hdr {
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u8 ver;
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@@ -2915,10 +3001,25 @@ enum fw_hdr_chip {
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FW_HDR_CHIP_T5
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};
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-#define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
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-#define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
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-#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
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-#define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
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+#define FW_HDR_FW_VER_MAJOR_S 24
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+#define FW_HDR_FW_VER_MAJOR_M 0xff
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+#define FW_HDR_FW_VER_MAJOR_G(x) \
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+ (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
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+
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+#define FW_HDR_FW_VER_MINOR_S 16
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+#define FW_HDR_FW_VER_MINOR_M 0xff
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+#define FW_HDR_FW_VER_MINOR_G(x) \
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+ (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
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+
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+#define FW_HDR_FW_VER_MICRO_S 8
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+#define FW_HDR_FW_VER_MICRO_M 0xff
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+#define FW_HDR_FW_VER_MICRO_G(x) \
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+ (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
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+
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+#define FW_HDR_FW_VER_BUILD_S 0
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+#define FW_HDR_FW_VER_BUILD_M 0xff
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+#define FW_HDR_FW_VER_BUILD_G(x) \
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+ (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
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enum fw_hdr_intfver {
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FW_HDR_INTFVER_NIC = 0x00,
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Hariprasad Shenai