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@@ -2805,20 +2805,13 @@ void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
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}
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#define IGU_CLEANUP_SLEEP_LENGTH (1000)
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-void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
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- struct qed_ptt *p_ptt,
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- u32 sb_id,
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- bool cleanup_set,
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- u16 opaque_fid
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- )
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+static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
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+ struct qed_ptt *p_ptt,
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+ u32 sb_id, bool cleanup_set, u16 opaque_fid)
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{
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+ u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
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u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
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u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
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- u32 data = 0;
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- u32 cmd_ctrl = 0;
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- u32 val = 0;
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- u32 sb_bit = 0;
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- u32 sb_bit_addr = 0;
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/* Set the data field */
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SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
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@@ -2863,11 +2856,9 @@ void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
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void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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- u32 sb_id,
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- u16 opaque,
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- bool b_set)
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+ u32 sb_id, u16 opaque, bool b_set)
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{
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- int pi;
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+ int pi, i;
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/* Set */
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if (b_set)
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@@ -2876,6 +2867,22 @@ void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
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/* Clear */
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qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
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+ /* Wait for the IGU SB to cleanup */
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+ for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
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+ u32 val;
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+
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+ val = qed_rd(p_hwfn, p_ptt,
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+ IGU_REG_WRITE_DONE_PENDING + ((sb_id / 32) * 4));
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+ if (val & (1 << (sb_id % 32)))
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+ usleep_range(10, 20);
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+ else
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+ break;
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+ }
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+ if (i == IGU_CLEANUP_SLEEP_LENGTH)
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+ DP_NOTICE(p_hwfn,
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+ "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
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+ sb_id);
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+
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/* Clear the CAU for the SB */
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for (pi = 0; pi < 12; pi++)
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qed_wr(p_hwfn, p_ptt,
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@@ -2884,13 +2891,11 @@ void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
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void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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- bool b_set,
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- bool b_slowpath)
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+ bool b_set, bool b_slowpath)
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{
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u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
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u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
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- u32 sb_id = 0;
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- u32 val = 0;
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+ u32 sb_id = 0, val = 0;
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val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
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val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
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@@ -2906,14 +2911,14 @@ void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
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p_hwfn->hw_info.opaque_fid,
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b_set);
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- if (b_slowpath) {
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- sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
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- DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
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- "IGU cleaning slowpath SB [%d]\n", sb_id);
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- qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
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- p_hwfn->hw_info.opaque_fid,
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- b_set);
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- }
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+ if (!b_slowpath)
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+ return;
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+
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+ sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
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+ DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
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+ "IGU cleaning slowpath SB [%d]\n", sb_id);
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+ qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
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+ p_hwfn->hw_info.opaque_fid, b_set);
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}
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static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
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