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@@ -105,7 +105,6 @@ acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr,
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addr_code = (base + pdesc->app_resident_code_offset) >> 8;
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addr_data = (base + pdesc->app_resident_data_offset) >> 8;
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- memset(desc, 0, sizeof(*desc));
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desc->ctx_dma = FALCON_DMAIDX_UCODE;
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desc->code_dma_base = lower_32_bits(addr_code);
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desc->non_sec_code_off = pdesc->app_resident_code_offset;
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@@ -354,6 +353,7 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs,
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&img->lsb_header, sizeof(img->lsb_header));
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/* Generate and write BL descriptor */
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+ memset(gdesc, 0, ls_func->bl_desc_size);
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ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
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nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off,
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@@ -515,7 +515,6 @@ acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
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struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc;
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u64 addr_code, addr_data;
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- memset(bl_desc, 0, sizeof(*bl_desc));
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addr_code = offset >> 8;
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addr_data = (offset + hdr->data_dma_base) >> 8;
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@@ -713,6 +712,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb,
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code_size, hsbl_desc->start_tag, 0, false);
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/* Generate the BL header */
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+ memset(bl_desc, 0, bl_desc_size);
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acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset);
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/*
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