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@@ -0,0 +1,28 @@
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+Cavium SuperSpeed DWC3 USB SoC controller
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+
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+Required properties:
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+- compatible: Should contain "cavium,octeon-7130-usb-uctl"
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+
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+Required child node:
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+A child node must exist to represent the core DWC3 IP block. The name of
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+the node is not important. The content of the node is defined in dwc3.txt.
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+
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+Example device node:
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+
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+ uctl@1180069000000 {
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+ compatible = "cavium,octeon-7130-usb-uctl";
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+ reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
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+ ranges;
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+ #address-cells = <0x00000002>;
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+ #size-cells = <0x00000002>;
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+ refclk-frequency = <0x05f5e100>;
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+ refclk-type-ss = "dlmc_ref_clk0";
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+ refclk-type-hs = "dlmc_ref_clk0";
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+ power = <0x00000002 0x00000002 0x00000001>;
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+ xhci@1690000000000 {
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+ compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3";
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+ reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
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+ interrupt-parent = <0x00000010>;
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+ interrupts = <0x00000009 0x00000004>;
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+ };
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+ };
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