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@@ -40,6 +40,24 @@
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* Co-processor emulation
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* Co-processor emulation
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*****************************************************************************/
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*****************************************************************************/
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+static bool write_to_read_only(struct kvm_vcpu *vcpu,
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+ const struct coproc_params *params)
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+{
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+ WARN_ONCE(1, "CP15 write to read-only register\n");
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+ print_cp_instr(params);
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+ kvm_inject_undefined(vcpu);
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+ return false;
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+}
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+
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+static bool read_from_write_only(struct kvm_vcpu *vcpu,
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+ const struct coproc_params *params)
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+{
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+ WARN_ONCE(1, "CP15 read to write-only register\n");
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+ print_cp_instr(params);
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+ kvm_inject_undefined(vcpu);
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+ return false;
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+}
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+
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/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
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/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
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static u32 cache_levels;
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static u32 cache_levels;
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