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@@ -209,12 +209,12 @@
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#define DMA_FECTL_IM (((u32)1) << 31)
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#define DMA_FECTL_IM (((u32)1) << 31)
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/* FSTS_REG */
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/* FSTS_REG */
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-#define DMA_FSTS_PPF ((u32)2)
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-#define DMA_FSTS_PFO ((u32)1)
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-#define DMA_FSTS_IQE (1 << 4)
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-#define DMA_FSTS_ICE (1 << 5)
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-#define DMA_FSTS_ITE (1 << 6)
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-#define DMA_FSTS_PRO (1 << 7)
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+#define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
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+#define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
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+#define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
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+#define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
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+#define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
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+#define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
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#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
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#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
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/* FRCD_REG, 32 bits access */
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/* FRCD_REG, 32 bits access */
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