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@@ -54,11 +54,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
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}
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}
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}
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}
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+static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
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+{
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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+ enum port port;
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+ u32 tmp;
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+
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+ for_each_dsi_port(port, intel_dsi->ports) {
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+ tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
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+ tmp |= COMBO_PHY_MODE_DSI;
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+ I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
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+ }
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+
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+ for_each_dsi_port(port, intel_dsi->ports) {
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+ intel_display_power_get(dev_priv, port == PORT_A ?
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+ POWER_DOMAIN_PORT_DDI_A_IO :
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+ POWER_DOMAIN_PORT_DDI_B_IO);
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+ }
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+}
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+
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static void __attribute__((unused))
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static void __attribute__((unused))
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gen11_dsi_pre_enable(struct intel_encoder *encoder,
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gen11_dsi_pre_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config,
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const struct intel_crtc_state *pipe_config,
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const struct drm_connector_state *conn_state)
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const struct drm_connector_state *conn_state)
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{
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{
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+ /* step2: enable IO power */
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+ gen11_dsi_enable_io_power(encoder);
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+
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/* step3: enable DSI PLL */
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/* step3: enable DSI PLL */
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gen11_dsi_program_esc_clk_div(encoder);
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gen11_dsi_program_esc_clk_div(encoder);
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}
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}
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