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@@ -137,10 +137,7 @@ u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw)
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{
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u32 head, tail;
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- if (!in_sw)
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- head = i40e_get_head(ring);
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- else
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- head = ring->next_to_clean;
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+ head = ring->next_to_clean;
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tail = readl(ring->tail);
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if (head != tail)
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@@ -165,7 +162,6 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
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{
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u16 i = tx_ring->next_to_clean;
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struct i40e_tx_buffer *tx_buf;
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- struct i40e_tx_desc *tx_head;
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struct i40e_tx_desc *tx_desc;
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unsigned int total_bytes = 0, total_packets = 0;
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unsigned int budget = vsi->work_limit;
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@@ -174,8 +170,6 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
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tx_desc = I40E_TX_DESC(tx_ring, i);
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i -= tx_ring->count;
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- tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
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-
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do {
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struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
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@@ -186,8 +180,9 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
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/* prevent any other reads prior to eop_desc */
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read_barrier_depends();
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- /* we have caught up to head, no work left to do */
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- if (tx_head == tx_desc)
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+ /* if the descriptor isn't done, no work yet to do */
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+ if (!(eop_desc->cmd_type_offset_bsz &
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+ cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
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break;
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/* clear next_to_watch to prevent false hangs */
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@@ -464,10 +459,6 @@ int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
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/* round up to nearest 4K */
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tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
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- /* add u32 for head writeback, align after this takes care of
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- * guaranteeing this is at least one cache line in size
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- */
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- tx_ring->size += sizeof(u32);
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tx_ring->size = ALIGN(tx_ring->size, 4096);
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tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
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&tx_ring->dma, GFP_KERNEL);
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@@ -2012,7 +2003,6 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
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u16 i = tx_ring->next_to_use;
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u32 td_tag = 0;
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dma_addr_t dma;
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- u16 desc_count = 1;
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if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
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td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
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@@ -2048,7 +2038,6 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
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tx_desc++;
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i++;
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- desc_count++;
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if (i == tx_ring->count) {
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tx_desc = I40E_TX_DESC(tx_ring, 0);
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@@ -2070,7 +2059,6 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
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tx_desc++;
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i++;
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- desc_count++;
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if (i == tx_ring->count) {
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tx_desc = I40E_TX_DESC(tx_ring, 0);
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@@ -2096,46 +2084,8 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
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i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
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- /* write last descriptor with EOP bit */
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- td_cmd |= I40E_TX_DESC_CMD_EOP;
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-
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- /* We can OR these values together as they both are checked against
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- * 4 below and at this point desc_count will be used as a boolean value
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- * after this if/else block.
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- */
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- desc_count |= ++tx_ring->packet_stride;
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-
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- /* Algorithm to optimize tail and RS bit setting:
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- * if queue is stopped
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- * mark RS bit
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- * reset packet counter
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- * else if xmit_more is supported and is true
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- * advance packet counter to 4
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- * reset desc_count to 0
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- *
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- * if desc_count >= 4
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- * mark RS bit
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- * reset packet counter
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- * if desc_count > 0
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- * update tail
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- *
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- * Note: If there are less than 4 descriptors
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- * pending and interrupts were disabled the service task will
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- * trigger a force WB.
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- */
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- if (netif_xmit_stopped(txring_txq(tx_ring))) {
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- goto do_rs;
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- } else if (skb->xmit_more) {
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- /* set stride to arm on next packet and reset desc_count */
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- tx_ring->packet_stride = WB_STRIDE;
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- desc_count = 0;
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- } else if (desc_count >= WB_STRIDE) {
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-do_rs:
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- /* write last descriptor with RS bit set */
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- td_cmd |= I40E_TX_DESC_CMD_RS;
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- tx_ring->packet_stride = 0;
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- }
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-
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+ /* write last descriptor with RS and EOP bits */
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+ td_cmd |= I40E_TXD_CMD;
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tx_desc->cmd_type_offset_bsz =
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build_ctob(td_cmd, td_offset, size, td_tag);
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@@ -2151,7 +2101,7 @@ do_rs:
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first->next_to_watch = tx_desc;
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/* notify HW of packet */
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- if (desc_count) {
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+ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
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writel(i, tx_ring->tail);
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/* we need this if more than one processor can write to our tail
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