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@@ -242,11 +242,6 @@ static void pcie_wait_link_active(struct controller *ctrl)
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__pcie_wait_link_active(ctrl, true);
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__pcie_wait_link_active(ctrl, true);
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}
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}
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-static void pcie_wait_link_not_active(struct controller *ctrl)
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-{
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- __pcie_wait_link_active(ctrl, false);
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-}
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-
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static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
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static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
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{
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{
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u32 l;
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u32 l;
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@@ -332,11 +327,6 @@ static int pciehp_link_enable(struct controller *ctrl)
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return __pciehp_link_set(ctrl, true);
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return __pciehp_link_set(ctrl, true);
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}
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}
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-static int pciehp_link_disable(struct controller *ctrl)
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-{
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- return __pciehp_link_set(ctrl, false);
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-}
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-
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void pciehp_get_attention_status(struct slot *slot, u8 *status)
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void pciehp_get_attention_status(struct slot *slot, u8 *status)
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{
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{
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struct controller *ctrl = slot->ctrl;
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struct controller *ctrl = slot->ctrl;
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@@ -508,14 +498,6 @@ void pciehp_power_off_slot(struct slot * slot)
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{
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{
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struct controller *ctrl = slot->ctrl;
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struct controller *ctrl = slot->ctrl;
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- /* Disable the link at first */
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- pciehp_link_disable(ctrl);
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- /* wait the link is down */
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- if (ctrl->link_active_reporting)
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- pcie_wait_link_not_active(ctrl);
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- else
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- msleep(1000);
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-
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pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
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pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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