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@@ -176,26 +176,15 @@ int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_irq_ops *ops = gvt->irq.ops;
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- u32 changed, masked, unmasked;
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u32 imr = *(u32 *)p_data;
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- gvt_dbg_irq("write IMR %x with val %x\n",
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- reg, imr);
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-
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- gvt_dbg_irq("old vIMR %x\n", vgpu_vreg(vgpu, reg));
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-
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- /* figure out newly masked/unmasked bits */
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- changed = vgpu_vreg(vgpu, reg) ^ imr;
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- masked = (vgpu_vreg(vgpu, reg) & changed) ^ changed;
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- unmasked = masked ^ changed;
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-
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- gvt_dbg_irq("changed %x, masked %x, unmasked %x\n",
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- changed, masked, unmasked);
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+ gvt_dbg_irq("write IMR %x, new %08x, old %08x, changed %08x\n",
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+ reg, imr, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ imr);
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vgpu_vreg(vgpu, reg) = imr;
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ops->check_pending_irq(vgpu);
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- gvt_dbg_irq("IRQ: new vIMR %x\n", vgpu_vreg(vgpu, reg));
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+
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return 0;
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}
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@@ -217,14 +206,11 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_irq_ops *ops = gvt->irq.ops;
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- u32 changed, enabled, disabled;
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u32 ier = *(u32 *)p_data;
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u32 virtual_ier = vgpu_vreg(vgpu, reg);
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- gvt_dbg_irq("write master irq reg %x with val %x\n",
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- reg, ier);
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-
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- gvt_dbg_irq("old vreg %x\n", vgpu_vreg(vgpu, reg));
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+ gvt_dbg_irq("write MASTER_IRQ %x, new %08x, old %08x, changed %08x\n",
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+ reg, ier, virtual_ier, virtual_ier ^ ier);
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/*
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* GEN8_MASTER_IRQ is a special irq register,
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@@ -236,16 +222,8 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
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vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
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vgpu_vreg(vgpu, reg) |= ier;
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- /* figure out newly enabled/disable bits */
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- changed = virtual_ier ^ ier;
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- enabled = (virtual_ier & changed) ^ changed;
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- disabled = enabled ^ changed;
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-
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- gvt_dbg_irq("changed %x, enabled %x, disabled %x\n",
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- changed, enabled, disabled);
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-
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ops->check_pending_irq(vgpu);
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- gvt_dbg_irq("new vreg %x\n", vgpu_vreg(vgpu, reg));
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+
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return 0;
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}
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@@ -268,21 +246,11 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_irq_ops *ops = gvt->irq.ops;
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struct intel_gvt_irq_info *info;
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- u32 changed, enabled, disabled;
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u32 ier = *(u32 *)p_data;
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- gvt_dbg_irq("write IER %x with val %x\n",
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- reg, ier);
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-
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- gvt_dbg_irq("old vIER %x\n", vgpu_vreg(vgpu, reg));
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+ gvt_dbg_irq("write IER %x, new %08x, old %08x, changed %08x\n",
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+ reg, ier, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ ier);
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- /* figure out newly enabled/disable bits */
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- changed = vgpu_vreg(vgpu, reg) ^ ier;
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- enabled = (vgpu_vreg(vgpu, reg) & changed) ^ changed;
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- disabled = enabled ^ changed;
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-
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- gvt_dbg_irq("changed %x, enabled %x, disabled %x\n",
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- changed, enabled, disabled);
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vgpu_vreg(vgpu, reg) = ier;
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info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
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@@ -293,7 +261,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
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update_upstream_irq(vgpu, info);
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ops->check_pending_irq(vgpu);
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- gvt_dbg_irq("new vIER %x\n", vgpu_vreg(vgpu, reg));
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+
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return 0;
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}
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@@ -317,7 +285,8 @@ int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
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iir_to_regbase(reg));
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u32 iir = *(u32 *)p_data;
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- gvt_dbg_irq("write IIR %x with val %x\n", reg, iir);
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+ gvt_dbg_irq("write IIR %x, new %08x, old %08x, changed %08x\n",
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+ reg, iir, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ iir);
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if (WARN_ON(!info))
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return -EINVAL;
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