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@@ -688,7 +688,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
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if (state == AMD_PG_STATE_GATE) {
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uvd_v4_2_stop(adev);
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- if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
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+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
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if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
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CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
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WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
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@@ -699,7 +699,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
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}
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return 0;
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} else {
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- if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
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+ if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) {
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if (RREG32_SMC(ixCURRENT_PG_STATUS) &
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CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
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WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
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