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@@ -437,6 +437,7 @@ static inline int check_io_access(struct pt_regs *regs)
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int machine_check_e500mc(struct pt_regs *regs)
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{
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unsigned long mcsr = mfspr(SPRN_MCSR);
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+ unsigned long pvr = mfspr(SPRN_PVR);
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unsigned long reason = mcsr;
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int recoverable = 1;
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@@ -478,8 +479,15 @@ int machine_check_e500mc(struct pt_regs *regs)
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* may still get logged and cause a machine check. We should
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* only treat the non-write shadow case as non-recoverable.
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*/
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- if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
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- recoverable = 0;
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+ /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
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+ * is not implemented but L1 data cache always runs in write
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+ * shadow mode. Hence on data cache parity errors HW will
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+ * automatically invalidate the L1 Data Cache.
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+ */
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+ if (PVR_VER(pvr) != PVR_VER_E6500) {
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+ if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
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+ recoverable = 0;
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+ }
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}
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if (reason & MCSR_L2MMU_MHIT) {
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