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@@ -3182,7 +3182,6 @@ static void
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i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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- uint32_t old_write_domain;
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if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
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return;
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@@ -3206,36 +3205,30 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
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if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
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POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base));
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- old_write_domain = obj->base.write_domain;
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- obj->base.write_domain = 0;
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-
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intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
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+ obj->base.write_domain = 0;
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trace_i915_gem_object_change_domain(obj,
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obj->base.read_domains,
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- old_write_domain);
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+ I915_GEM_DOMAIN_GTT);
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}
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/** Flushes the CPU write domain for the object if it's dirty. */
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static void
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i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
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{
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- uint32_t old_write_domain;
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-
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if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
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return;
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if (i915_gem_clflush_object(obj, obj->pin_display))
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i915_gem_chipset_flush(to_i915(obj->base.dev));
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- old_write_domain = obj->base.write_domain;
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- obj->base.write_domain = 0;
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-
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intel_fb_obj_flush(obj, false, ORIGIN_CPU);
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+ obj->base.write_domain = 0;
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trace_i915_gem_object_change_domain(obj,
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obj->base.read_domains,
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- old_write_domain);
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+ I915_GEM_DOMAIN_CPU);
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}
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/**
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