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@@ -4,216 +4,147 @@ config MIPS
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# Horrible source of confusion. Die, die, die ...
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select EMBEDDED
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-# shouldn't it be per-subarchitecture?
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-config ARCH_MAY_HAVE_PC_FDC
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- bool
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- default y
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-
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mainmenu "Linux/MIPS Kernel Configuration"
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source "init/Kconfig"
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-config SYS_SUPPORTS_32BIT_KERNEL
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- bool
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-config SYS_SUPPORTS_64BIT_KERNEL
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- bool
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-config CPU_SUPPORTS_32BIT_KERNEL
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- bool
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-config CPU_SUPPORTS_64BIT_KERNEL
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- bool
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-
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-menu "Kernel type"
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-
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-choice
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-
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- prompt "Kernel code model"
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- help
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- You should only select this option if you have a workload that
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- actually benefits from 64-bit processing or if your machine has
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- large memory. You will only be presented a single option in this
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- menu if your system does not support both 32-bit and 64-bit kernels.
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-
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-config 32BIT
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- bool "32-bit kernel"
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- depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
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- select TRAD_SIGNALS
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- help
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- Select this option if you want to build a 32-bit kernel.
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-
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-config 64BIT
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- bool "64-bit kernel"
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- depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
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- help
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- Select this option if you want to build a 64-bit kernel.
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-
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-endchoice
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-
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-endmenu
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-
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menu "Machine selection"
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-config MACH_JAZZ
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- bool "Support for the Jazz family of machines"
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- select ARC
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- select ARC32
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- select GENERIC_ISA_DMA
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- select I8259
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- select ISA
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- select SYS_SUPPORTS_32BIT_KERNEL
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- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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- help
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- This a family of machines based on the MIPS R4030 chipset which was
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- used by several vendors to build RISC/os and Windows NT workstations.
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- Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
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- Olivetti M700-10 workstations.
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+choice
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+ prompt "System type"
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+ default SGI_IP22
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-config ACER_PICA_61
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- bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
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- depends on MACH_JAZZ && EXPERIMENTAL
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+config MIPS_MTX1
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+ bool "Support for 4G Systems MTX-1 board"
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select DMA_NONCOHERENT
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- help
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- This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
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- kernel that runs on these, say Y here. For details about Linux on
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- the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
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- <http://www.linux-mips.org/>.
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+ select HW_HAS_PCI
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+ select SOC_AU1500
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config MIPS_MAGNUM_4000
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- bool "Support for MIPS Magnum 4000"
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- depends on MACH_JAZZ
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+config MIPS_BOSPORUS
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+ bool "AMD Alchemy Bosporus board"
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+ select SOC_AU1500
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select DMA_NONCOHERENT
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- help
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- This is a machine with a R4000 100 MHz CPU. To compile a Linux
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- kernel that runs on these, say Y here. For details about Linux on
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- the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
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- <http://www.linux-mips.org/>.
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config OLIVETTI_M700
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- bool "Support for Olivetti M700-10"
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- depends on MACH_JAZZ
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+config MIPS_PB1000
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+ bool "AMD Alchemy PB1000 board"
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+ select SOC_AU1000
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select DMA_NONCOHERENT
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- help
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- This is a machine with a R4000 100 MHz CPU. To compile a Linux
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- kernel that runs on these, say Y here. For details about Linux on
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- the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
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- <http://www.linux-mips.org/>.
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-
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-config MACH_VR41XX
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- bool "Support for NEC VR4100 series based machines"
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- select SYS_SUPPORTS_32BIT_KERNEL
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- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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+ select HW_HAS_PCI
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+ select SWAP_IO_SPACE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config NEC_CMBVR4133
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- bool "Support for NEC CMB-VR4133"
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- depends on MACH_VR41XX
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- select CPU_VR41XX
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+config MIPS_PB1100
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+ bool "AMD Alchemy PB1100 board"
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+ select SOC_AU1100
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select DMA_NONCOHERENT
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- select IRQ_CPU
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select HW_HAS_PCI
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+ select SWAP_IO_SPACE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config ROCKHOPPER
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- bool "Support for Rockhopper baseboard"
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- depends on NEC_CMBVR4133
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- select I8259
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- select HAVE_STD_PC_SERIAL_PORT
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+config MIPS_PB1500
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+ bool "AMD Alchemy PB1500 board"
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+ select SOC_AU1500
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+ select DMA_NONCOHERENT
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+ select HW_HAS_PCI
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config CASIO_E55
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- bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
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- depends on MACH_VR41XX
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- select CPU_LITTLE_ENDIAN
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+config MIPS_PB1550
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+ bool "AMD Alchemy PB1550 board"
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+ select SOC_AU1550
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select DMA_NONCOHERENT
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- select IRQ_CPU
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- select ISA
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+ select HW_HAS_PCI
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+ select MIPS_DISABLE_OBSOLETE_IDE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config IBM_WORKPAD
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- bool "Support for IBM WorkPad z50"
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- depends on MACH_VR41XX
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- select CPU_LITTLE_ENDIAN
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+config MIPS_PB1200
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+ bool "AMD Alchemy PB1200 board"
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+ select SOC_AU1200
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select DMA_NONCOHERENT
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- select IRQ_CPU
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- select ISA
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+ select MIPS_DISABLE_OBSOLETE_IDE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config TANBAC_TB022X
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- bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
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- depends on MACH_VR41XX
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- select CPU_LITTLE_ENDIAN
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+config MIPS_DB1000
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+ bool "AMD Alchemy DB1000 board"
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+ select SOC_AU1000
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select DMA_NONCOHERENT
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- select IRQ_CPU
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select HW_HAS_PCI
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- help
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- The TANBAC VR4131 multichip module(TB0225) and
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- the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
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- manufactured by TANBAC.
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- Please refer to <http://www.tanbac.co.jp/>
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- about VR4131 multichip module and VR4131DIMM.
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config TANBAC_TB0226
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- bool "Support for TANBAC Mbase(TB0226)"
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- depends on TANBAC_TB022X
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- select GPIO_VR41XX
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- help
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- The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC.
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- Please refer to <http://www.tanbac.co.jp/> about Mbase.
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-
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-config TANBAC_TB0287
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- bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
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- depends on TANBAC_TB022X
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- help
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- The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform manufactured by TANBAC.
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- Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
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-
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-config VICTOR_MPC30X
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- bool "Support for Victor MP-C303/304"
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- depends on MACH_VR41XX
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- select CPU_LITTLE_ENDIAN
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+config MIPS_DB1100
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+ bool "AMD Alchemy DB1100 board"
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+ select SOC_AU1100
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select DMA_NONCOHERENT
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- select IRQ_CPU
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- select HW_HAS_PCI
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config ZAO_CAPCELLA
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- bool "Support for ZAO Networks Capcella"
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- depends on MACH_VR41XX
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- select CPU_LITTLE_ENDIAN
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+config MIPS_DB1500
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+ bool "AMD Alchemy DB1500 board"
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+ select SOC_AU1500
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select DMA_NONCOHERENT
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- select IRQ_CPU
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select HW_HAS_PCI
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+ select MIPS_DISABLE_OBSOLETE_IDE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_BIG_ENDIAN
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config PCI_VR41XX
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- bool "Add PCI control unit support of NEC VR4100 series"
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- depends on MACH_VR41XX && HW_HAS_PCI
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- default y
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- select PCI
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+config MIPS_DB1550
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+ bool "AMD Alchemy DB1550 board"
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+ select SOC_AU1550
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+ select HW_HAS_PCI
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+ select DMA_NONCOHERENT
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+ select MIPS_DISABLE_OBSOLETE_IDE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config VRC4173
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- tristate "Add NEC VRC4173 companion chip support"
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- depends on MACH_VR41XX && PCI_VR41XX
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- ---help---
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- The NEC VRC4173 is a companion chip for NEC VR4122/VR4131.
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+config MIPS_DB1200
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+ bool "AMD Alchemy DB1200 board"
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+ select SOC_AU1200
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+ select DMA_COHERENT
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+ select MIPS_DISABLE_OBSOLETE_IDE
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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-config TOSHIBA_JMR3927
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- bool "Support for Toshiba JMR-TX3927 board"
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+config MIPS_MIRAGE
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+ bool "AMD Alchemy Mirage board"
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select DMA_NONCOHERENT
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- select HW_HAS_PCI
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- select SWAP_IO_SPACE
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- select SYS_SUPPORTS_32BIT_KERNEL
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+ select SOC_AU1500
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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config MIPS_COBALT
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bool "Support for Cobalt Server"
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- depends on EXPERIMENTAL
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select I8259
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select IRQ_CPU
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+ select MIPS_GT64111
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+ select SYS_HAS_CPU_NEVADA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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config MACH_DECSTATION
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bool "Support for DECstations"
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select BOOT_ELF32
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select DMA_NONCOHERENT
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+ select EARLY_PRINTK
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select IRQ_CPU
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+ select SYS_HAS_CPU_R3000
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+ select SYS_HAS_CPU_R4X00
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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- ---help---
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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+ help
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This enables support for DEC's MIPS based workstations. For details
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see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
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DECstation porting pages on <http://decstation.unix-ag.org/>.
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@@ -234,8 +165,10 @@ config MIPS_EV64120
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select MIPS_GT64120
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+ select SYS_HAS_CPU_R5000
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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+ select SYS_SUPPORTS_BIG_ENDIAN
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help
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This is an evaluation board based on the Galileo GT-64120
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single-chip system controller that contains a MIPS R5000 compatible
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@@ -243,10 +176,6 @@ config MIPS_EV64120
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<http://www.marvell.com/>. Say Y here if you wish to build a
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kernel for this platform.
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-config EVB_PCI1
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- bool "Enable Second PCI (PCI1)"
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- depends on MIPS_EV64120
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-
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config MIPS_EV96100
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bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
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depends on EXPERIMENTAL
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@@ -256,8 +185,11 @@ config MIPS_EV96100
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select MIPS_GT96100
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select RM7000_CPU_SCACHE
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select SWAP_IO_SPACE
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+ select SYS_HAS_CPU_R5000
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+ select SYS_HAS_CPU_RM7000
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select SYS_SUPPORTS_32BIT_KERNEL
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- select SYS_SUPPORTS_64BIT_KERNEL
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+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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+ select SYS_SUPPORTS_BIG_ENDIAN
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help
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This is an evaluation board based on the Galileo GT-96100 LAN/WAN
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communications controllers containing a MIPS R5000 compatible core
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@@ -268,8 +200,11 @@ config MIPS_IVR
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bool "Support for Globespan IVR board"
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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+ select ITE_BOARD_GEN
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+ select SYS_HAS_CPU_NEVADA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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This is an evaluation board built by Globespan to showcase thir
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iVR (Internet Video Recorder) design. It utilizes a QED RM5231
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@@ -277,37 +212,16 @@ config MIPS_IVR
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located at <http://www.globespan.net/>. Say Y here if you wish to
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build a kernel for this platform.
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-config LASAT
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- bool "Support for LASAT Networks platforms"
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- select DMA_NONCOHERENT
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- select HW_HAS_PCI
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- select MIPS_GT64120
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- select R5000_CPU_SCACHE
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- select SYS_SUPPORTS_32BIT_KERNEL
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- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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-
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-config PICVUE
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- tristate "PICVUE LCD display driver"
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- depends on LASAT
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-
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-config PICVUE_PROC
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- tristate "PICVUE LCD display driver /proc interface"
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- depends on PICVUE
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-
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-config DS1603
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- bool "DS1603 RTC driver"
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- depends on LASAT
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-
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-config LASAT_SYSCTL
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- bool "LASAT sysctl interface"
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- depends on LASAT
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-
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config MIPS_ITE8172
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bool "Support for ITE 8172G board"
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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+ select ITE_BOARD_GEN
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+ select SYS_HAS_CPU_R5432
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+ select SYS_HAS_CPU_NEVADA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
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with ATX form factor that utilizes a MIPS R5000 to work with its
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@@ -315,42 +229,86 @@ config MIPS_ITE8172
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|
either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
|
|
|
a kernel for this platform.
|
|
|
|
|
|
-config IT8172_REVC
|
|
|
- bool "Support for older IT8172 (Rev C)"
|
|
|
- depends on MIPS_ITE8172
|
|
|
+config MACH_JAZZ
|
|
|
+ bool "Support for the Jazz family of machines"
|
|
|
+ select ARC
|
|
|
+ select ARC32
|
|
|
+ select ARCH_MAY_HAVE_PC_FDC
|
|
|
+ select GENERIC_ISA_DMA
|
|
|
+ select I8259
|
|
|
+ select ISA
|
|
|
+ select SYS_HAS_CPU_R4X00
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
help
|
|
|
- Say Y here to support the older, Revision C version of the Integrated
|
|
|
- Technology Express, Inc. ITE8172 SBC. Vendor page at
|
|
|
- <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
|
|
|
- board at <http://www.mvista.com/partners/semiconductor/ite.html>.
|
|
|
+ This a family of machines based on the MIPS R4030 chipset which was
|
|
|
+ used by several vendors to build RISC/os and Windows NT workstations.
|
|
|
+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
|
|
|
+ Olivetti M700-10 workstations.
|
|
|
+
|
|
|
+config LASAT
|
|
|
+ bool "Support for LASAT Networks platforms"
|
|
|
+ select DMA_NONCOHERENT
|
|
|
+ select HW_HAS_PCI
|
|
|
+ select MIPS_GT64120
|
|
|
+ select MIPS_NILE4
|
|
|
+ select R5000_CPU_SCACHE
|
|
|
+ select SYS_HAS_CPU_R5000
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config MIPS_ATLAS
|
|
|
bool "Support for MIPS Atlas board"
|
|
|
select BOOT_ELF32
|
|
|
select DMA_NONCOHERENT
|
|
|
+ select IRQ_CPU
|
|
|
select HW_HAS_PCI
|
|
|
+ select MIPS_BOARDS_GEN
|
|
|
+ select MIPS_BONITO64
|
|
|
select MIPS_GT64120
|
|
|
+ select MIPS_MSC
|
|
|
+ select RM7000_CPU_SCACHE
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_MIPS32_R1
|
|
|
+ select SYS_HAS_CPU_MIPS32_R2
|
|
|
+ select SYS_HAS_CPU_MIPS64_R1
|
|
|
+ select SYS_HAS_CPU_NEVADA
|
|
|
+ select SYS_HAS_CPU_RM7000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
- This enables support for the QED R5231-based MIPS Atlas evaluation
|
|
|
+ This enables support for the MIPS Technologies Atlas evaluation
|
|
|
board.
|
|
|
|
|
|
config MIPS_MALTA
|
|
|
bool "Support for MIPS Malta board"
|
|
|
+ select ARCH_MAY_HAVE_PC_FDC
|
|
|
select BOOT_ELF32
|
|
|
select HAVE_STD_PC_SERIAL_PORT
|
|
|
select DMA_NONCOHERENT
|
|
|
+ select IRQ_CPU
|
|
|
select GENERIC_ISA_DMA
|
|
|
select HW_HAS_PCI
|
|
|
select I8259
|
|
|
+ select MIPS_BOARDS_GEN
|
|
|
+ select MIPS_BONITO64
|
|
|
select MIPS_GT64120
|
|
|
+ select MIPS_MSC
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_MIPS32_R1
|
|
|
+ select SYS_HAS_CPU_MIPS32_R2
|
|
|
+ select SYS_HAS_CPU_MIPS64_R1
|
|
|
+ select SYS_HAS_CPU_NEVADA
|
|
|
+ select SYS_HAS_CPU_RM7000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
- This enables support for the VR5000-based MIPS Malta evaluation
|
|
|
+ This enables support for the MIPS Technologies Malta evaluation
|
|
|
board.
|
|
|
|
|
|
config MIPS_SEAD
|
|
@@ -358,50 +316,64 @@ config MIPS_SEAD
|
|
|
depends on EXPERIMENTAL
|
|
|
select IRQ_CPU
|
|
|
select DMA_NONCOHERENT
|
|
|
+ select MIPS_BOARDS_GEN
|
|
|
+ select SYS_HAS_CPU_MIPS32_R1
|
|
|
+ select SYS_HAS_CPU_MIPS32_R2
|
|
|
+ select SYS_HAS_CPU_MIPS64_R1
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
- select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
+ help
|
|
|
+ This enables support for the MIPS Technologies SEAD evaluation
|
|
|
+ board.
|
|
|
|
|
|
-config MOMENCO_OCELOT
|
|
|
- bool "Support for Momentum Ocelot board"
|
|
|
+config MIPS_SIM
|
|
|
+ bool 'Support for MIPS simulator (MIPSsim)'
|
|
|
select DMA_NONCOHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
- select IRQ_CPU_RM7K
|
|
|
- select MIPS_GT64120
|
|
|
- select RM7000_CPU_SCACHE
|
|
|
- select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_MIPS32_R1
|
|
|
+ select SYS_HAS_CPU_MIPS32_R2
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
- select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
|
|
- Momentum Computer <http://www.momenco.com/>.
|
|
|
+ This option enables support for MIPS Technologies MIPSsim software
|
|
|
+ emulator.
|
|
|
|
|
|
-config MOMENCO_OCELOT_G
|
|
|
- bool "Support for Momentum Ocelot-G board"
|
|
|
+config MOMENCO_JAGUAR_ATX
|
|
|
+ bool "Support for Momentum Jaguar board"
|
|
|
+ select BOOT_ELF32
|
|
|
select DMA_NONCOHERENT
|
|
|
select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
select IRQ_CPU_RM7K
|
|
|
+ select IRQ_MV64340
|
|
|
+ select LIMITED_DMA
|
|
|
select PCI_MARVELL
|
|
|
select RM7000_CPU_SCACHE
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_RM9000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
|
|
+ The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
|
|
|
Momentum Computer <http://www.momenco.com/>.
|
|
|
|
|
|
-config MOMENCO_OCELOT_C
|
|
|
- bool "Support for Momentum Ocelot-C board"
|
|
|
+config MOMENCO_OCELOT
|
|
|
+ bool "Support for Momentum Ocelot board"
|
|
|
select DMA_NONCOHERENT
|
|
|
select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
- select IRQ_MV64340
|
|
|
- select PCI_MARVELL
|
|
|
+ select IRQ_CPU_RM7K
|
|
|
+ select MIPS_GT64120
|
|
|
select RM7000_CPU_SCACHE
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_RM7000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
|
|
Momentum Computer <http://www.momenco.com/>.
|
|
@@ -417,80 +389,95 @@ config MOMENCO_OCELOT_3
|
|
|
select PCI_MARVELL
|
|
|
select RM7000_CPU_SCACHE
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_RM9000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
The Ocelot-3 is based off Discovery III System Controller and
|
|
|
PMC-Sierra Rm79000 core.
|
|
|
|
|
|
-config MOMENCO_JAGUAR_ATX
|
|
|
- bool "Support for Momentum Jaguar board"
|
|
|
- select BOOT_ELF32
|
|
|
+config MOMENCO_OCELOT_C
|
|
|
+ bool "Support for Momentum Ocelot-C board"
|
|
|
select DMA_NONCOHERENT
|
|
|
select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
- select IRQ_CPU_RM7K
|
|
|
select IRQ_MV64340
|
|
|
- select LIMITED_DMA
|
|
|
select PCI_MARVELL
|
|
|
select RM7000_CPU_SCACHE
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_RM7000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
- The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
|
|
|
+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
|
|
Momentum Computer <http://www.momenco.com/>.
|
|
|
|
|
|
-config JAGUAR_DMALOW
|
|
|
- bool "Low DMA Mode"
|
|
|
- depends on MOMENCO_JAGUAR_ATX
|
|
|
- help
|
|
|
- Select to Y if jump JP5 is set on your board, N otherwise. Normally
|
|
|
- the jumper is set, so if you feel unsafe, just say Y.
|
|
|
-
|
|
|
-config PMC_YOSEMITE
|
|
|
- bool "Support for PMC-Sierra Yosemite eval board"
|
|
|
- select DMA_COHERENT
|
|
|
+config MOMENCO_OCELOT_G
|
|
|
+ bool "Support for Momentum Ocelot-G board"
|
|
|
+ select DMA_NONCOHERENT
|
|
|
select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
select IRQ_CPU_RM7K
|
|
|
- select IRQ_CPU_RM9K
|
|
|
+ select PCI_MARVELL
|
|
|
+ select RM7000_CPU_SCACHE
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_RM7000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
- Yosemite is an evaluation board for the RM9000x2 processor
|
|
|
- manufactured by PMC-Sierra
|
|
|
+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
|
|
+ Momentum Computer <http://www.momenco.com/>.
|
|
|
+
|
|
|
+config MIPS_XXS1500
|
|
|
+ bool "Support for MyCable XXS1500 board"
|
|
|
+ select DMA_NONCOHERENT
|
|
|
+ select SOC_AU1500
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
-config HYPERTRANSPORT
|
|
|
- bool "Hypertransport Support for PMC-Sierra Yosemite"
|
|
|
- depends on PMC_YOSEMITE
|
|
|
+config PNX8550_V2PCI
|
|
|
+ bool "Support for Philips PNX8550 based Viper2-PCI board"
|
|
|
+ select PNX8550
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
+
|
|
|
+config PNX8550_JBS
|
|
|
+ bool "Support for Philips PNX8550 based JBS board"
|
|
|
+ select PNX8550
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config DDB5074
|
|
|
bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
|
|
|
depends on EXPERIMENTAL
|
|
|
+ select DDB5XXX_COMMON
|
|
|
select DMA_NONCOHERENT
|
|
|
select HAVE_STD_PC_SERIAL_PORT
|
|
|
select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
select I8259
|
|
|
select ISA
|
|
|
+ select SYS_HAS_CPU_R5000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
- select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
This enables support for the VR5000-based NEC DDB Vrc-5074
|
|
|
evaluation board.
|
|
|
|
|
|
config DDB5476
|
|
|
bool "Support for NEC DDB Vrc-5476"
|
|
|
+ select DDB5XXX_COMMON
|
|
|
select DMA_NONCOHERENT
|
|
|
select HAVE_STD_PC_SERIAL_PORT
|
|
|
select HW_HAS_PCI
|
|
|
select IRQ_CPU
|
|
|
select I8259
|
|
|
select ISA
|
|
|
+ select SYS_HAS_CPU_R5432
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
This enables support for the R5432-based NEC DDB Vrc-5476
|
|
|
evaluation board.
|
|
@@ -501,12 +488,15 @@ config DDB5476
|
|
|
|
|
|
config DDB5477
|
|
|
bool "Support for NEC DDB Vrc-5477"
|
|
|
+ select DDB5XXX_COMMON
|
|
|
select DMA_NONCOHERENT
|
|
|
select HW_HAS_PCI
|
|
|
select I8259
|
|
|
select IRQ_CPU
|
|
|
+ select SYS_HAS_CPU_R5432
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
This enables support for the R5432-based NEC DDB Vrc-5477,
|
|
|
or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
|
|
@@ -514,10 +504,28 @@ config DDB5477
|
|
|
Features : kernel debugging, serial terminal, NFS root fs, on-board
|
|
|
ether port USB, AC97, PCI, etc.
|
|
|
|
|
|
-config DDB5477_BUS_FREQUENCY
|
|
|
- int "bus frequency (in kHZ, 0 for auto-detect)"
|
|
|
- depends on DDB5477
|
|
|
- default 0
|
|
|
+config MACH_VR41XX
|
|
|
+ bool "Support for NEC VR4100 series based machines"
|
|
|
+ select SYS_HAS_CPU_VR41XX
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+
|
|
|
+config PMC_YOSEMITE
|
|
|
+ bool "Support for PMC-Sierra Yosemite eval board"
|
|
|
+ select DMA_COHERENT
|
|
|
+ select HW_HAS_PCI
|
|
|
+ select IRQ_CPU
|
|
|
+ select IRQ_CPU_RM7K
|
|
|
+ select IRQ_CPU_RM9K
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_RM9000
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
+ help
|
|
|
+ Yosemite is an evaluation board for the RM9000x2 processor
|
|
|
+ manufactured by PMC-Sierra.
|
|
|
|
|
|
config QEMU
|
|
|
bool "Support for Qemu"
|
|
@@ -527,15 +535,16 @@ config QEMU
|
|
|
select I8259
|
|
|
select ISA
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_MIPS32_R1
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
- Qemu is a software emulator which among other architectures also
|
|
|
- can simulate a MIPS32 4Kc system. This patch adds support for the
|
|
|
- system architecture that currently is being simulated by Qemu. It
|
|
|
- will eventually be removed again when Qemu has the capability to
|
|
|
- simulate actual MIPS hardware platforms. More information on Qemu
|
|
|
- can be found at http://www.linux-mips.org/wiki/Qemu.
|
|
|
+ Qemu is a software emulator which among other architectures also
|
|
|
+ can simulate a MIPS32 4Kc system. This patch adds support for the
|
|
|
+ system architecture that currently is being simulated by Qemu. It
|
|
|
+ will eventually be removed again when Qemu has the capability to
|
|
|
+ simulate actual MIPS hardware platforms. More information on Qemu
|
|
|
+ can be found at http://www.linux-mips.org/wiki/Qemu.
|
|
|
|
|
|
config SGI_IP22
|
|
|
bool "Support for SGI IP22 (Indy/Indigo2)"
|
|
@@ -543,11 +552,15 @@ config SGI_IP22
|
|
|
select ARC32
|
|
|
select BOOT_ELF32
|
|
|
select DMA_NONCOHERENT
|
|
|
+ select HW_HAS_EISA
|
|
|
select IP22_CPU_SCACHE
|
|
|
select IRQ_CPU
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_R4X00
|
|
|
+ select SYS_HAS_CPU_R5000
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
This are the SGI Indy, Challenge S and Indigo2, as well as certain
|
|
|
OEM variants like the Tandem CMN B006S. To compile a Linux kernel
|
|
@@ -557,70 +570,18 @@ config SGI_IP27
|
|
|
bool "Support for SGI IP27 (Origin200/2000)"
|
|
|
select ARC
|
|
|
select ARC64
|
|
|
+ select BOOT_ELF64
|
|
|
select DMA_IP27
|
|
|
select HW_HAS_PCI
|
|
|
select PCI_DOMAINS
|
|
|
+ select SYS_HAS_CPU_R10000
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
|
|
|
workstations. To compile a Linux kernel that runs on these, say Y
|
|
|
here.
|
|
|
|
|
|
-#config SGI_SN0_XXL
|
|
|
-# bool "IP27 XXL"
|
|
|
-# depends on SGI_IP27
|
|
|
-# This options adds support for userspace processes upto 16TB size.
|
|
|
-# Normally the limit is just .5TB.
|
|
|
-
|
|
|
-config SGI_SN0_N_MODE
|
|
|
- bool "IP27 N-Mode"
|
|
|
- depends on SGI_IP27
|
|
|
- help
|
|
|
- The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
|
|
|
- configured in either N-Modes which allows for more nodes or M-Mode
|
|
|
- which allows for more memory. Your system is most probably
|
|
|
- running in M-Mode, so you should say N here.
|
|
|
-
|
|
|
-config ARCH_DISCONTIGMEM_ENABLE
|
|
|
- bool
|
|
|
- default y if SGI_IP27
|
|
|
- help
|
|
|
- Say Y to upport efficient handling of discontiguous physical memory,
|
|
|
- for architectures which are either NUMA (Non-Uniform Memory Access)
|
|
|
- or have huge holes in the physical address space for other reasons.
|
|
|
- See <file:Documentation/vm/numa> for more.
|
|
|
-
|
|
|
-config NUMA
|
|
|
- bool "NUMA Support"
|
|
|
- depends on SGI_IP27
|
|
|
- help
|
|
|
- Say Y to compile the kernel to support NUMA (Non-Uniform Memory
|
|
|
- Access). This option is for configuring high-end multiprocessor
|
|
|
- server machines. If in doubt, say N.
|
|
|
-
|
|
|
-config MAPPED_KERNEL
|
|
|
- bool "Mapped kernel support"
|
|
|
- depends on SGI_IP27
|
|
|
- help
|
|
|
- Change the way a Linux kernel is loaded into memory on a MIPS64
|
|
|
- machine. This is required in order to support text replication and
|
|
|
- NUMA. If you need to understand it, read the source code.
|
|
|
-
|
|
|
-config REPLICATE_KTEXT
|
|
|
- bool "Kernel text replication support"
|
|
|
- depends on SGI_IP27
|
|
|
- help
|
|
|
- Say Y here to enable replicating the kernel text across multiple
|
|
|
- nodes in a NUMA cluster. This trades memory for speed.
|
|
|
-
|
|
|
-config REPLICATE_EXHANDLERS
|
|
|
- bool "Exception handler replication support"
|
|
|
- depends on SGI_IP27
|
|
|
- help
|
|
|
- Say Y here to enable replicating the kernel exception handlers
|
|
|
- across multiple nodes in a NUMA cluster. This trades memory for
|
|
|
- speed.
|
|
|
-
|
|
|
config SGI_IP32
|
|
|
bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
|
|
|
depends on EXPERIMENTAL
|
|
@@ -633,353 +594,152 @@ config SGI_IP32
|
|
|
select HW_HAS_PCI
|
|
|
select R5000_CPU_SCACHE
|
|
|
select RM7000_CPU_SCACHE
|
|
|
+ select SYS_HAS_CPU_R5000
|
|
|
+ select SYS_HAS_CPU_R10000 if BROKEN
|
|
|
+ select SYS_HAS_CPU_RM7000
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
help
|
|
|
If you want this kernel to run on SGI O2 workstation, say Y here.
|
|
|
|
|
|
-config SOC_AU1X00
|
|
|
- bool "Support for AMD/Alchemy Au1X00 SOCs"
|
|
|
- select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
-
|
|
|
-choice
|
|
|
- prompt "Au1X00 SOC Type"
|
|
|
- depends on SOC_AU1X00
|
|
|
- help
|
|
|
- Say Y here to enable support for one of three AMD/Alchemy
|
|
|
- SOCs. For additional documentation see www.amd.com.
|
|
|
-
|
|
|
-config SOC_AU1000
|
|
|
- bool "SOC_AU1000"
|
|
|
-config SOC_AU1100
|
|
|
- bool "SOC_AU1100"
|
|
|
-config SOC_AU1500
|
|
|
- bool "SOC_AU1500"
|
|
|
-config SOC_AU1550
|
|
|
- bool "SOC_AU1550"
|
|
|
-
|
|
|
-endchoice
|
|
|
-
|
|
|
-choice
|
|
|
- prompt "AMD/Alchemy Au1x00 board support"
|
|
|
- depends on SOC_AU1X00
|
|
|
- help
|
|
|
- These are evaluation boards built by AMD/Alchemy to
|
|
|
- showcase their Au1X00 Internet Edge Processors. The SOC design
|
|
|
- is based on the MIPS32 architecture running at 266/400/500MHz
|
|
|
- with many integrated peripherals. Further information can be
|
|
|
- found at their website, <http://www.amd.com/>. Say Y here if you
|
|
|
- wish to build a kernel for this platform.
|
|
|
-
|
|
|
-config MIPS_PB1000
|
|
|
- bool "PB1000 board"
|
|
|
- depends on SOC_AU1000
|
|
|
- select DMA_NONCOHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
- select SWAP_IO_SPACE
|
|
|
-
|
|
|
-config MIPS_PB1100
|
|
|
- bool "PB1100 board"
|
|
|
- depends on SOC_AU1100
|
|
|
- select DMA_NONCOHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
- select SWAP_IO_SPACE
|
|
|
-
|
|
|
-config MIPS_PB1500
|
|
|
- bool "PB1500 board"
|
|
|
- depends on SOC_AU1500
|
|
|
- select DMA_COHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
-
|
|
|
-config MIPS_PB1550
|
|
|
- bool "PB1550 board"
|
|
|
- depends on SOC_AU1550
|
|
|
- select DMA_COHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
- select MIPS_DISABLE_OBSOLETE_IDE
|
|
|
-
|
|
|
-config MIPS_DB1000
|
|
|
- bool "DB1000 board"
|
|
|
- depends on SOC_AU1000
|
|
|
- select DMA_NONCOHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
-
|
|
|
-config MIPS_DB1100
|
|
|
- bool "DB1100 board"
|
|
|
- depends on SOC_AU1100
|
|
|
- select DMA_NONCOHERENT
|
|
|
-
|
|
|
-config MIPS_DB1500
|
|
|
- bool "DB1500 board"
|
|
|
- depends on SOC_AU1500
|
|
|
- select DMA_COHERENT
|
|
|
- select HW_HAS_PCI
|
|
|
- select MIPS_DISABLE_OBSOLETE_IDE
|
|
|
-
|
|
|
-config MIPS_DB1550
|
|
|
- bool "DB1550 board"
|
|
|
- depends on SOC_AU1550
|
|
|
- select HW_HAS_PCI
|
|
|
- select DMA_COHERENT
|
|
|
- select MIPS_DISABLE_OBSOLETE_IDE
|
|
|
-
|
|
|
-config MIPS_BOSPORUS
|
|
|
- bool "Bosporus board"
|
|
|
- depends on SOC_AU1500
|
|
|
- select DMA_NONCOHERENT
|
|
|
-
|
|
|
-config MIPS_MIRAGE
|
|
|
- bool "Mirage board"
|
|
|
- depends on SOC_AU1500
|
|
|
- select DMA_NONCOHERENT
|
|
|
-
|
|
|
-config MIPS_XXS1500
|
|
|
- bool "MyCable XXS1500 board"
|
|
|
- depends on SOC_AU1500
|
|
|
- select DMA_NONCOHERENT
|
|
|
-
|
|
|
-config MIPS_MTX1
|
|
|
- bool "4G Systems MTX-1 board"
|
|
|
- depends on SOC_AU1500
|
|
|
- select HW_HAS_PCI
|
|
|
- select DMA_NONCOHERENT
|
|
|
-
|
|
|
-endchoice
|
|
|
-
|
|
|
-config SIBYTE_SB1xxx_SOC
|
|
|
- bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
|
|
|
- depends on EXPERIMENTAL
|
|
|
+config SIBYTE_BIGSUR
|
|
|
+ bool "Support for Sibyte BigSur"
|
|
|
select BOOT_ELF32
|
|
|
select DMA_COHERENT
|
|
|
+ select PCI_DOMAINS
|
|
|
+ select SIBYTE_BCM1x80
|
|
|
select SWAP_IO_SPACE
|
|
|
- select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
- select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
-
|
|
|
-choice
|
|
|
- prompt "BCM1xxx SOC-based board"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
- default SIBYTE_SWARM
|
|
|
- help
|
|
|
- Enable support for boards based on the SiByte line of SOCs
|
|
|
- from Broadcom. There are configurations for the known
|
|
|
- evaluation boards, or you can choose "Other" and add your
|
|
|
- own board support code.
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_SWARM
|
|
|
- bool "BCM91250A-SWARM"
|
|
|
+ bool "Support for Sibyte BCM91250A-SWARM"
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_SB1250
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_SENTOSA
|
|
|
- bool "BCM91250E-Sentosa"
|
|
|
+ bool "Support for Sibyte BCM91250E-Sentosa"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_SB1250
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_RHONE
|
|
|
- bool "BCM91125E-Rhone"
|
|
|
+ bool "Support for Sibyte BCM91125E-Rhone"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_BCM1125H
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_CARMEL
|
|
|
- bool "BCM91120x-Carmel"
|
|
|
+ bool "Support for Sibyte BCM91120x-Carmel"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_BCM1120
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_PTSWARM
|
|
|
- bool "BCM91250PT-PTSWARM"
|
|
|
+ bool "Support for Sibyte BCM91250PT-PTSWARM"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_SB1250
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_LITTLESUR
|
|
|
- bool "BCM91250C2-LittleSur"
|
|
|
+ bool "Support for Sibyte BCM91250C2-LittleSur"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_SB1250
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_CRHINE
|
|
|
- bool "BCM91120C-CRhine"
|
|
|
+ bool "Support for Sibyte BCM91120C-CRhine"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_BCM1120
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SIBYTE_CRHONE
|
|
|
- bool "BCM91125C-CRhone"
|
|
|
- select SIBYTE_BCM1125
|
|
|
-
|
|
|
-config SIBYTE_UNKNOWN
|
|
|
- bool "Other"
|
|
|
-
|
|
|
-endchoice
|
|
|
-
|
|
|
-config SIBYTE_BOARD
|
|
|
- bool
|
|
|
- depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN
|
|
|
- default y
|
|
|
-
|
|
|
-choice
|
|
|
- prompt "BCM1xxx SOC Type"
|
|
|
- depends on SIBYTE_UNKNOWN
|
|
|
- default SIBYTE_UNK_BCM1250
|
|
|
- help
|
|
|
- Since you haven't chosen a known evaluation board from
|
|
|
- Broadcom, you must explicitly pick the SOC this kernel is
|
|
|
- targetted for.
|
|
|
-
|
|
|
-config SIBYTE_UNK_BCM1250
|
|
|
- bool "BCM1250"
|
|
|
- select SIBYTE_SB1250
|
|
|
-
|
|
|
-config SIBYTE_UNK_BCM1120
|
|
|
- bool "BCM1120"
|
|
|
- select SIBYTE_BCM1120
|
|
|
-
|
|
|
-config SIBYTE_UNK_BCM1125
|
|
|
- bool "BCM1125"
|
|
|
+ bool "Support for Sibyte BCM91125C-CRhone"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ select BOOT_ELF32
|
|
|
+ select DMA_COHERENT
|
|
|
select SIBYTE_BCM1125
|
|
|
-
|
|
|
-config SIBYTE_UNK_BCM1125H
|
|
|
- bool "BCM1125H"
|
|
|
- select SIBYTE_BCM1125H
|
|
|
-
|
|
|
-endchoice
|
|
|
-
|
|
|
-config SIBYTE_SB1250
|
|
|
- bool
|
|
|
- select HW_HAS_PCI
|
|
|
-
|
|
|
-config SIBYTE_BCM1120
|
|
|
- bool
|
|
|
- select SIBYTE_BCM112X
|
|
|
-
|
|
|
-config SIBYTE_BCM1125
|
|
|
- bool
|
|
|
- select HW_HAS_PCI
|
|
|
- select SIBYTE_BCM112X
|
|
|
-
|
|
|
-config SIBYTE_BCM1125H
|
|
|
- bool
|
|
|
- select HW_HAS_PCI
|
|
|
- select SIBYTE_BCM112X
|
|
|
-
|
|
|
-config SIBYTE_BCM112X
|
|
|
- bool
|
|
|
-
|
|
|
-choice
|
|
|
- prompt "SiByte SOC Stepping"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
-
|
|
|
-config CPU_SB1_PASS_1
|
|
|
- bool "1250 Pass1"
|
|
|
- depends on SIBYTE_SB1250
|
|
|
- select CPU_HAS_PREFETCH
|
|
|
-
|
|
|
-config CPU_SB1_PASS_2_1250
|
|
|
- bool "1250 An"
|
|
|
- depends on SIBYTE_SB1250
|
|
|
- select CPU_SB1_PASS_2
|
|
|
- help
|
|
|
- Also called BCM1250 Pass 2
|
|
|
-
|
|
|
-config CPU_SB1_PASS_2_2
|
|
|
- bool "1250 Bn"
|
|
|
- depends on SIBYTE_SB1250
|
|
|
- select CPU_HAS_PREFETCH
|
|
|
- help
|
|
|
- Also called BCM1250 Pass 2.2
|
|
|
-
|
|
|
-config CPU_SB1_PASS_4
|
|
|
- bool "1250 Cn"
|
|
|
- depends on SIBYTE_SB1250
|
|
|
- select CPU_HAS_PREFETCH
|
|
|
- help
|
|
|
- Also called BCM1250 Pass 3
|
|
|
-
|
|
|
-config CPU_SB1_PASS_2_112x
|
|
|
- bool "112x Hybrid"
|
|
|
- depends on SIBYTE_BCM112X
|
|
|
- select CPU_SB1_PASS_2
|
|
|
-
|
|
|
-config CPU_SB1_PASS_3
|
|
|
- bool "112x An"
|
|
|
- depends on SIBYTE_BCM112X
|
|
|
- select CPU_HAS_PREFETCH
|
|
|
-
|
|
|
-endchoice
|
|
|
-
|
|
|
-config CPU_SB1_PASS_2
|
|
|
- bool
|
|
|
-
|
|
|
-config SIBYTE_HAS_LDT
|
|
|
- bool
|
|
|
- depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
|
|
|
- default y
|
|
|
-
|
|
|
-config SIMULATION
|
|
|
- bool "Running under simulation"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
- help
|
|
|
- Build a kernel suitable for running under the GDB simulator.
|
|
|
- Primarily adjusts the kernel's notion of time.
|
|
|
-
|
|
|
-config SIBYTE_CFE
|
|
|
- bool "Booting from CFE"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
- help
|
|
|
- Make use of the CFE API for enumerating available memory,
|
|
|
- controlling secondary CPUs, and possibly console output.
|
|
|
-
|
|
|
-config SIBYTE_CFE_CONSOLE
|
|
|
- bool "Use firmware console"
|
|
|
- depends on SIBYTE_CFE
|
|
|
- help
|
|
|
- Use the CFE API's console write routines during boot. Other console
|
|
|
- options (VT console, sb1250 duart console, etc.) should not be
|
|
|
- configured.
|
|
|
-
|
|
|
-config SIBYTE_STANDALONE
|
|
|
- bool
|
|
|
- depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
|
|
|
- default y
|
|
|
-
|
|
|
-config SIBYTE_STANDALONE_RAM_SIZE
|
|
|
- int "Memory size (in megabytes)"
|
|
|
- depends on SIBYTE_STANDALONE
|
|
|
- default "32"
|
|
|
-
|
|
|
-config SIBYTE_BUS_WATCHER
|
|
|
- bool "Support for Bus Watcher statistics"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
- help
|
|
|
- Handle and keep statistics on the bus error interrupts (COR_ECC,
|
|
|
- BAD_ECC, IO_BUS).
|
|
|
-
|
|
|
-config SIBYTE_BW_TRACE
|
|
|
- bool "Capture bus trace before bus error"
|
|
|
- depends on SIBYTE_BUS_WATCHER
|
|
|
- help
|
|
|
- Run a continuous bus trace, dumping the raw data as soon as
|
|
|
- a ZBbus error is detected. Cannot work if ZBbus profiling
|
|
|
- is turned on, and also will interfere with JTAG-based trace
|
|
|
- buffer activity. Raw buffer data is dumped to console, and
|
|
|
- must be processed off-line.
|
|
|
-
|
|
|
-config SIBYTE_SB1250_PROF
|
|
|
- bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
-
|
|
|
-config SIBYTE_TBPROF
|
|
|
- bool "Support for ZBbus profiling"
|
|
|
- depends on SIBYTE_SB1xxx_SOC
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_SB1
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
|
|
|
config SNI_RM200_PCI
|
|
|
bool "Support for SNI RM200 PCI"
|
|
|
select ARC
|
|
|
select ARC32
|
|
|
+ select ARCH_MAY_HAVE_PC_FDC
|
|
|
select BOOT_ELF32
|
|
|
select DMA_NONCOHERENT
|
|
|
select GENERIC_ISA_DMA
|
|
|
select HAVE_STD_PC_SERIAL_PORT
|
|
|
+ select HW_HAS_EISA
|
|
|
select HW_HAS_PCI
|
|
|
select I8259
|
|
|
select ISA
|
|
|
+ select SYS_HAS_CPU_R4X00
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
help
|
|
|
The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
|
|
|
Nixdorf Informationssysteme (SNI), parent company of Pyramid
|
|
|
Technology and now in turn merged with Fujitsu. Say Y here to
|
|
|
support this machine type.
|
|
|
|
|
|
+config TOSHIBA_JMR3927
|
|
|
+ bool "Support for Toshiba JMR-TX3927 board"
|
|
|
+ select DMA_NONCOHERENT
|
|
|
+ select HW_HAS_PCI
|
|
|
+ select MIPS_TX3927
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_TX39XX
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select TOSHIBA_BOARDS
|
|
|
+
|
|
|
config TOSHIBA_RBTX4927
|
|
|
bool "Support for Toshiba TBTX49[23]7 board"
|
|
|
select DMA_NONCOHERENT
|
|
@@ -988,15 +748,51 @@ config TOSHIBA_RBTX4927
|
|
|
select I8259
|
|
|
select ISA
|
|
|
select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_TX49XX
|
|
|
select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
select SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select TOSHIBA_BOARDS
|
|
|
help
|
|
|
This Toshiba board is based on the TX4927 processor. Say Y here to
|
|
|
support this machine type
|
|
|
|
|
|
-config TOSHIBA_FPCIB0
|
|
|
- bool "FPCIB0 Backplane Support"
|
|
|
- depends on TOSHIBA_RBTX4927
|
|
|
+config TOSHIBA_RBTX4938
|
|
|
+ bool "Support for Toshiba RBTX4938 board"
|
|
|
+ select HAVE_STD_PC_SERIAL_PORT
|
|
|
+ select DMA_NONCOHERENT
|
|
|
+ select GENERIC_ISA_DMA
|
|
|
+ select HAS_TXX9_SERIAL
|
|
|
+ select HW_HAS_PCI
|
|
|
+ select I8259
|
|
|
+ select ISA
|
|
|
+ select SWAP_IO_SPACE
|
|
|
+ select SYS_HAS_CPU_TX49XX
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
+ select SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ select TOSHIBA_BOARDS
|
|
|
+ help
|
|
|
+ This Toshiba board is based on the TX4938 processor. Say Y here to
|
|
|
+ support this machine type
|
|
|
+
|
|
|
+endchoice
|
|
|
+
|
|
|
+source "arch/mips/ddb5xxx/Kconfig"
|
|
|
+source "arch/mips/gt64120/ev64120/Kconfig"
|
|
|
+source "arch/mips/jazz/Kconfig"
|
|
|
+source "arch/mips/ite-boards/Kconfig"
|
|
|
+source "arch/mips/lasat/Kconfig"
|
|
|
+source "arch/mips/momentum/Kconfig"
|
|
|
+source "arch/mips/pmc-sierra/Kconfig"
|
|
|
+source "arch/mips/sgi-ip27/Kconfig"
|
|
|
+source "arch/mips/sibyte/Kconfig"
|
|
|
+source "arch/mips/tx4927/Kconfig"
|
|
|
+source "arch/mips/tx4938/Kconfig"
|
|
|
+source "arch/mips/vr41xx/Kconfig"
|
|
|
+source "arch/mips/philips/pnx8550/common/Kconfig"
|
|
|
+
|
|
|
+endmenu
|
|
|
|
|
|
config RWSEM_GENERIC_SPINLOCK
|
|
|
bool
|
|
@@ -1014,8 +810,9 @@ config GENERIC_CALIBRATE_DELAY
|
|
|
#
|
|
|
config ARC
|
|
|
bool
|
|
|
- depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
|
|
|
- default y
|
|
|
+
|
|
|
+config ARCH_MAY_HAVE_PC_FDC
|
|
|
+ bool
|
|
|
|
|
|
config DMA_COHERENT
|
|
|
bool
|
|
@@ -1034,51 +831,65 @@ config DMA_NONCOHERENT
|
|
|
config DMA_NEED_PCI_MAP_STATE
|
|
|
bool
|
|
|
|
|
|
+config OWN_DMA
|
|
|
+ bool
|
|
|
+
|
|
|
config EARLY_PRINTK
|
|
|
bool
|
|
|
- depends on MACH_DECSTATION
|
|
|
- default y
|
|
|
|
|
|
config GENERIC_ISA_DMA
|
|
|
bool
|
|
|
- depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA
|
|
|
- default y
|
|
|
|
|
|
config I8259
|
|
|
bool
|
|
|
- depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT
|
|
|
- default y
|
|
|
|
|
|
config LIMITED_DMA
|
|
|
bool
|
|
|
select HIGHMEM
|
|
|
+ select SYS_SUPPORTS_HIGHMEM
|
|
|
|
|
|
config MIPS_BONITO64
|
|
|
bool
|
|
|
- depends on MIPS_ATLAS || MIPS_MALTA
|
|
|
- default y
|
|
|
|
|
|
config MIPS_MSC
|
|
|
bool
|
|
|
- depends on MIPS_ATLAS || MIPS_MALTA
|
|
|
- default y
|
|
|
|
|
|
config MIPS_NILE4
|
|
|
bool
|
|
|
- depends on LASAT
|
|
|
- default y
|
|
|
|
|
|
config MIPS_DISABLE_OBSOLETE_IDE
|
|
|
bool
|
|
|
|
|
|
-config CPU_LITTLE_ENDIAN
|
|
|
- bool "Generate little endian code"
|
|
|
- default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
|
|
|
- default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
|
|
|
+#
|
|
|
+# Endianess selection. Suffiently obscure so many users don't know what to
|
|
|
+# answer,so we try hard to limit the available choices. Also the use of a
|
|
|
+# choice statement should be more obvious to the user.
|
|
|
+#
|
|
|
+choice
|
|
|
+ prompt "Endianess selection"
|
|
|
help
|
|
|
Some MIPS machines can be configured for either little or big endian
|
|
|
- byte order. These modes require different kernels. Say Y if your
|
|
|
- machine is little endian, N if it's a big endian machine.
|
|
|
+ byte order. These modes require different kernels and a different
|
|
|
+ Linux distribution. In general there is one prefered byteorder for a
|
|
|
+ particular system but some systems are just as commonly used in the
|
|
|
+ one or the other endianess.
|
|
|
+
|
|
|
+config CPU_BIG_ENDIAN
|
|
|
+ bool "Big endian"
|
|
|
+ depends on SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+
|
|
|
+config CPU_LITTLE_ENDIAN
|
|
|
+ bool "Little endian"
|
|
|
+ depends on SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
+ help
|
|
|
+
|
|
|
+endchoice
|
|
|
+
|
|
|
+config SYS_SUPPORTS_BIG_ENDIAN
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_SUPPORTS_LITTLE_ENDIAN
|
|
|
+ bool
|
|
|
|
|
|
config IRQ_CPU
|
|
|
bool
|
|
@@ -1086,42 +897,69 @@ config IRQ_CPU
|
|
|
config IRQ_CPU_RM7K
|
|
|
bool
|
|
|
|
|
|
+config IRQ_CPU_RM9K
|
|
|
+ bool
|
|
|
+
|
|
|
config IRQ_MV64340
|
|
|
bool
|
|
|
|
|
|
config DDB5XXX_COMMON
|
|
|
bool
|
|
|
- depends on DDB5074 || DDB5476 || DDB5477
|
|
|
- default y
|
|
|
|
|
|
config MIPS_BOARDS_GEN
|
|
|
bool
|
|
|
- depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD
|
|
|
- default y
|
|
|
|
|
|
config MIPS_GT64111
|
|
|
bool
|
|
|
- depends on MIPS_COBALT
|
|
|
- default y
|
|
|
|
|
|
config MIPS_GT64120
|
|
|
bool
|
|
|
- depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT
|
|
|
- default y
|
|
|
|
|
|
config MIPS_TX3927
|
|
|
bool
|
|
|
- depends on TOSHIBA_JMR3927
|
|
|
select HAS_TXX9_SERIAL
|
|
|
- default y
|
|
|
|
|
|
config PCI_MARVELL
|
|
|
bool
|
|
|
|
|
|
config ITE_BOARD_GEN
|
|
|
bool
|
|
|
- depends on MIPS_IVR || MIPS_ITE8172
|
|
|
- default y
|
|
|
+
|
|
|
+config SOC_AU1000
|
|
|
+ bool
|
|
|
+ select SOC_AU1X00
|
|
|
+
|
|
|
+config SOC_AU1100
|
|
|
+ bool
|
|
|
+ select SOC_AU1X00
|
|
|
+
|
|
|
+config SOC_AU1500
|
|
|
+ bool
|
|
|
+ select SOC_AU1X00
|
|
|
+
|
|
|
+config SOC_AU1550
|
|
|
+ bool
|
|
|
+ select SOC_AU1X00
|
|
|
+
|
|
|
+config SOC_AU1200
|
|
|
+ bool
|
|
|
+ select SOC_AU1X00
|
|
|
+
|
|
|
+config SOC_AU1X00
|
|
|
+ bool
|
|
|
+ select SYS_HAS_CPU_MIPS32_R1
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+
|
|
|
+config PNX8550
|
|
|
+ bool
|
|
|
+ select SOC_PNX8550
|
|
|
+
|
|
|
+config SOC_PNX8550
|
|
|
+ bool
|
|
|
+ select DMA_NONCOHERENT
|
|
|
+ select HW_HAS_PCI
|
|
|
+ select SYS_HAS_CPU_R4X00
|
|
|
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
|
|
|
|
config SWAP_IO_SPACE
|
|
|
bool
|
|
@@ -1148,6 +986,9 @@ config SYSCLK_100
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
+config ARC32
|
|
|
+ bool
|
|
|
+
|
|
|
config AU1X00_USB_DEVICE
|
|
|
bool
|
|
|
depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
|
|
@@ -1155,11 +996,7 @@ config AU1X00_USB_DEVICE
|
|
|
|
|
|
config MIPS_GT96100
|
|
|
bool
|
|
|
- depends on MIPS_EV96100
|
|
|
- default y
|
|
|
- help
|
|
|
- Say Y here to support the Galileo Technology GT96100 communications
|
|
|
- controller card. There is a web page at <http://www.galileot.com/>.
|
|
|
+ select MIPS_GT64120
|
|
|
|
|
|
config IT8172_CIR
|
|
|
bool
|
|
@@ -1173,8 +1010,6 @@ config IT8712
|
|
|
|
|
|
config BOOT_ELF32
|
|
|
bool
|
|
|
- depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI
|
|
|
- default y
|
|
|
|
|
|
config MIPS_L1_CACHE_SHIFT
|
|
|
int
|
|
@@ -1182,11 +1017,6 @@ config MIPS_L1_CACHE_SHIFT
|
|
|
default "7" if SGI_IP27
|
|
|
default "5"
|
|
|
|
|
|
-config ARC32
|
|
|
- bool
|
|
|
- depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
|
|
|
- default y
|
|
|
-
|
|
|
config HAVE_STD_PC_SERIAL_PORT
|
|
|
bool
|
|
|
|
|
@@ -1206,30 +1036,12 @@ config ARC_PROMLIB
|
|
|
|
|
|
config ARC64
|
|
|
bool
|
|
|
- depends on SGI_IP27
|
|
|
- default y
|
|
|
|
|
|
config BOOT_ELF64
|
|
|
bool
|
|
|
- depends on SGI_IP27
|
|
|
- default y
|
|
|
-
|
|
|
-#config MAPPED_PCI_IO y
|
|
|
-# bool
|
|
|
-# depends on SGI_IP27
|
|
|
-# default y
|
|
|
-
|
|
|
-config QL_ISP_A64
|
|
|
- bool
|
|
|
- depends on SGI_IP27
|
|
|
- default y
|
|
|
|
|
|
config TOSHIBA_BOARDS
|
|
|
bool
|
|
|
- depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
|
|
|
- default y
|
|
|
-
|
|
|
-endmenu
|
|
|
|
|
|
menu "CPU selection"
|
|
|
|
|
@@ -1237,18 +1049,69 @@ choice
|
|
|
prompt "CPU type"
|
|
|
default CPU_R4X00
|
|
|
|
|
|
-config CPU_MIPS32
|
|
|
- bool "MIPS32"
|
|
|
+config CPU_MIPS32_R1
|
|
|
+ bool "MIPS32 Release 1"
|
|
|
+ depends on SYS_HAS_CPU_MIPS32_R1
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
+ select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
+ help
|
|
|
+ Choose this option to build a kernel for release 1 or later of the
|
|
|
+ MIPS32 architecture. Most modern embedded systems with a 32-bit
|
|
|
+ MIPS processor are based on a MIPS32 processor. If you know the
|
|
|
+ specific type of processor in your system, choose those that one
|
|
|
+ otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
|
|
|
+ Release 2 of the MIPS32 architecture is available since several
|
|
|
+ years so chances are you even have a MIPS32 Release 2 processor
|
|
|
+ in which case you should choose CPU_MIPS32_R2 instead for better
|
|
|
+ performance.
|
|
|
+
|
|
|
+config CPU_MIPS32_R2
|
|
|
+ bool "MIPS32 Release 2"
|
|
|
+ depends on SYS_HAS_CPU_MIPS32_R2
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
+ help
|
|
|
+ Choose this option to build a kernel for release 2 or later of the
|
|
|
+ MIPS32 architecture. Most modern embedded systems with a 32-bit
|
|
|
+ MIPS processor are based on a MIPS32 processor. If you know the
|
|
|
+ specific type of processor in your system, choose those that one
|
|
|
+ otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
|
|
|
|
|
|
-config CPU_MIPS64
|
|
|
- bool "MIPS64"
|
|
|
+config CPU_MIPS64_R1
|
|
|
+ bool "MIPS64 Release 1"
|
|
|
+ depends on SYS_HAS_CPU_MIPS64_R1
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
+ select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ help
|
|
|
+ Choose this option to build a kernel for release 1 or later of the
|
|
|
+ MIPS64 architecture. Many modern embedded systems with a 64-bit
|
|
|
+ MIPS processor are based on a MIPS64 processor. If you know the
|
|
|
+ specific type of processor in your system, choose those that one
|
|
|
+ otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
|
|
|
+ Release 2 of the MIPS64 architecture is available since several
|
|
|
+ years so chances are you even have a MIPS64 Release 2 processor
|
|
|
+ in which case you should choose CPU_MIPS64_R2 instead for better
|
|
|
+ performance.
|
|
|
+
|
|
|
+config CPU_MIPS64_R2
|
|
|
+ bool "MIPS64 Release 2"
|
|
|
+ depends on SYS_HAS_CPU_MIPS64_R2
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ help
|
|
|
+ Choose this option to build a kernel for release 2 or later of the
|
|
|
+ MIPS64 architecture. Many modern embedded systems with a 64-bit
|
|
|
+ MIPS processor are based on a MIPS64 processor. If you know the
|
|
|
+ specific type of processor in your system, choose those that one
|
|
|
+ otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
|
|
|
|
|
|
config CPU_R3000
|
|
|
bool "R3000"
|
|
|
+ depends on SYS_HAS_CPU_R3000
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_HIGHMEM
|
|
|
help
|
|
|
Please make sure to pick the right CPU type. Linux/MIPS is not
|
|
|
designed to be generic, i.e. Kernels compiled for R3000 CPUs will
|
|
@@ -1259,20 +1122,23 @@ config CPU_R3000
|
|
|
|
|
|
config CPU_TX39XX
|
|
|
bool "R39XX"
|
|
|
+ depends on SYS_HAS_CPU_TX39XX
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
|
|
|
config CPU_VR41XX
|
|
|
bool "R41xx"
|
|
|
+ depends on SYS_HAS_CPU_VR41XX
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
help
|
|
|
- The options selects support for the NEC VR41xx series of processors.
|
|
|
+ The options selects support for the NEC VR4100 series of processors.
|
|
|
Only choose this option if you have one of these processors as a
|
|
|
kernel built with this option will not run on any other type of
|
|
|
processor or vice versa.
|
|
|
|
|
|
config CPU_R4300
|
|
|
bool "R4300"
|
|
|
+ depends on SYS_HAS_CPU_R4300
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
help
|
|
@@ -1280,6 +1146,7 @@ config CPU_R4300
|
|
|
|
|
|
config CPU_R4X00
|
|
|
bool "R4x00"
|
|
|
+ depends on SYS_HAS_CPU_R4X00
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
help
|
|
@@ -1288,11 +1155,13 @@ config CPU_R4X00
|
|
|
|
|
|
config CPU_TX49XX
|
|
|
bool "R49XX"
|
|
|
+ depends on SYS_HAS_CPU_TX49XX
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
|
|
|
config CPU_R5000
|
|
|
bool "R5000"
|
|
|
+ depends on SYS_HAS_CPU_R5000
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
help
|
|
@@ -1300,10 +1169,14 @@ config CPU_R5000
|
|
|
|
|
|
config CPU_R5432
|
|
|
bool "R5432"
|
|
|
+ depends on SYS_HAS_CPU_R5432
|
|
|
+ select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
|
|
|
config CPU_R6000
|
|
|
bool "R6000"
|
|
|
depends on EXPERIMENTAL
|
|
|
+ depends on SYS_HAS_CPU_R6000
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
help
|
|
|
MIPS Technologies R6000 and R6000A series processors. Note these
|
|
@@ -1311,6 +1184,7 @@ config CPU_R6000
|
|
|
|
|
|
config CPU_NEVADA
|
|
|
bool "RM52xx"
|
|
|
+ depends on SYS_HAS_CPU_NEVADA
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
help
|
|
@@ -1319,6 +1193,8 @@ config CPU_NEVADA
|
|
|
config CPU_R8000
|
|
|
bool "R8000"
|
|
|
depends on EXPERIMENTAL
|
|
|
+ depends on SYS_HAS_CPU_R8000
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
help
|
|
|
MIPS Technologies R8000 processors. Note these processors are
|
|
@@ -1326,25 +1202,151 @@ config CPU_R8000
|
|
|
|
|
|
config CPU_R10000
|
|
|
bool "R10000"
|
|
|
+ depends on SYS_HAS_CPU_R10000
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_HIGHMEM
|
|
|
help
|
|
|
MIPS Technologies R10000-series processors.
|
|
|
|
|
|
config CPU_RM7000
|
|
|
bool "RM7000"
|
|
|
+ depends on SYS_HAS_CPU_RM7000
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_HIGHMEM
|
|
|
|
|
|
config CPU_RM9000
|
|
|
bool "RM9000"
|
|
|
+ depends on SYS_HAS_CPU_RM9000
|
|
|
+ select CPU_HAS_PREFETCH
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_HIGHMEM
|
|
|
|
|
|
config CPU_SB1
|
|
|
bool "SB1"
|
|
|
+ depends on SYS_HAS_CPU_SB1
|
|
|
select CPU_SUPPORTS_32BIT_KERNEL
|
|
|
select CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ select CPU_SUPPORTS_HIGHMEM
|
|
|
+
|
|
|
+endchoice
|
|
|
+
|
|
|
+config SYS_HAS_CPU_MIPS32_R1
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_MIPS32_R2
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_MIPS64_R1
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_MIPS64_R2
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R3000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_TX39XX
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_VR41XX
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R4300
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R4X00
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_TX49XX
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R5000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R5432
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R6000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_NEVADA
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R8000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_R10000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_RM7000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_RM9000
|
|
|
+ bool
|
|
|
+
|
|
|
+config SYS_HAS_CPU_SB1
|
|
|
+ bool
|
|
|
+
|
|
|
+endmenu
|
|
|
+
|
|
|
+#
|
|
|
+# These two indicate any levelof the MIPS32 and MIPS64 architecture
|
|
|
+#
|
|
|
+config CPU_MIPS32
|
|
|
+ bool
|
|
|
+ default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
|
|
|
+
|
|
|
+config CPU_MIPS64
|
|
|
+ bool
|
|
|
+ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
|
|
|
+
|
|
|
+#
|
|
|
+# These two indicate the revision of the architecture, either 32 bot 64 bit.
|
|
|
+#
|
|
|
+config CPU_MIPSR1
|
|
|
+ bool
|
|
|
+ default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
|
|
|
+
|
|
|
+config CPU_MIPSR2
|
|
|
+ bool
|
|
|
+ default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
|
|
|
+
|
|
|
+config SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ bool
|
|
|
+config SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ bool
|
|
|
+config CPU_SUPPORTS_32BIT_KERNEL
|
|
|
+ bool
|
|
|
+config CPU_SUPPORTS_64BIT_KERNEL
|
|
|
+ bool
|
|
|
+
|
|
|
+menu "Kernel type"
|
|
|
+
|
|
|
+choice
|
|
|
+
|
|
|
+ prompt "Kernel code model"
|
|
|
+ help
|
|
|
+ You should only select this option if you have a workload that
|
|
|
+ actually benefits from 64-bit processing or if your machine has
|
|
|
+ large memory. You will only be presented a single option in this
|
|
|
+ menu if your system does not support both 32-bit and 64-bit kernels.
|
|
|
+
|
|
|
+config 32BIT
|
|
|
+ bool "32-bit kernel"
|
|
|
+ depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
|
|
|
+ select TRAD_SIGNALS
|
|
|
+ help
|
|
|
+ Select this option if you want to build a 32-bit kernel.
|
|
|
+config 64BIT
|
|
|
+ bool "64-bit kernel"
|
|
|
+ depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
|
|
|
+ help
|
|
|
+ Select this option if you want to build a 64-bit kernel.
|
|
|
|
|
|
endchoice
|
|
|
|
|
@@ -1416,12 +1418,43 @@ config SIBYTE_DMA_PAGEOPS
|
|
|
SiByte Linux port. Seems to give a small performance benefit.
|
|
|
|
|
|
config CPU_HAS_PREFETCH
|
|
|
- bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2
|
|
|
- default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000
|
|
|
+ bool
|
|
|
+
|
|
|
+config MIPS_MT
|
|
|
+ bool "Enable MIPS MT"
|
|
|
|
|
|
-config VTAG_ICACHE
|
|
|
- bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32
|
|
|
- default y if CPU_SB1
|
|
|
+choice
|
|
|
+ prompt "MIPS MT options"
|
|
|
+ depends on MIPS_MT
|
|
|
+
|
|
|
+config MIPS_MT_SMP
|
|
|
+ bool "Use 1 TC on each available VPE for SMP"
|
|
|
+ select SMP
|
|
|
+
|
|
|
+config MIPS_VPE_LOADER
|
|
|
+ bool "VPE loader support."
|
|
|
+ depends on MIPS_MT
|
|
|
+ help
|
|
|
+ Includes a loader for loading an elf relocatable object
|
|
|
+ onto another VPE and running it.
|
|
|
+
|
|
|
+endchoice
|
|
|
+
|
|
|
+config MIPS_VPE_LOADER_TOM
|
|
|
+ bool "Load VPE program into memory hidden from linux"
|
|
|
+ depends on MIPS_VPE_LOADER
|
|
|
+ default y
|
|
|
+ help
|
|
|
+ The loader can use memory that is present but has been hidden from
|
|
|
+ Linux using the kernel command line option "mem=xxMB". It's up to
|
|
|
+ you to ensure the amount you put in the option and the space your
|
|
|
+ program requires is less or equal to the amount physically present.
|
|
|
+
|
|
|
+# this should possibly be in drivers/char, but it is rather cpu related. Hmmm
|
|
|
+config MIPS_VPE_APSP_API
|
|
|
+ bool "Enable support for AP/SP API (RTLX)"
|
|
|
+ depends on MIPS_VPE_LOADER
|
|
|
+ help
|
|
|
|
|
|
config SB1_PASS_1_WORKAROUNDS
|
|
|
bool
|
|
@@ -1440,7 +1473,7 @@ config SB1_PASS_2_1_WORKAROUNDS
|
|
|
|
|
|
config 64BIT_PHYS_ADDR
|
|
|
bool "Support for 64-bit physical address space"
|
|
|
- depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
|
|
|
+ depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT
|
|
|
|
|
|
config CPU_ADVANCED
|
|
|
bool "Override CPU Options"
|
|
@@ -1463,7 +1496,7 @@ config CPU_HAS_LLSC
|
|
|
|
|
|
config CPU_HAS_LLDSCD
|
|
|
bool "lld/scd Instructions available" if CPU_ADVANCED
|
|
|
- default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32
|
|
|
+ default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
|
|
|
help
|
|
|
Say Y here if your CPU has the lld and scd instructions, the 64-bit
|
|
|
equivalents of ll and sc. Say Y here for better performance, N if
|
|
@@ -1477,11 +1510,51 @@ config CPU_HAS_WB
|
|
|
machines which require flushing of write buffers in software. Saying
|
|
|
Y is the safe option; N may result in kernel malfunction and crashes.
|
|
|
|
|
|
+menu "MIPSR2 Interrupt handling"
|
|
|
+ depends on CPU_MIPSR2 && CPU_ADVANCED
|
|
|
+
|
|
|
+config CPU_MIPSR2_IRQ_VI
|
|
|
+ bool "Vectored interrupt mode"
|
|
|
+ help
|
|
|
+ Vectored interrupt mode allowing faster dispatching of interrupts.
|
|
|
+ The board support code needs to be written to take advantage of this
|
|
|
+ mode. Compatibility code is included to allow the kernel to run on
|
|
|
+ a CPU that does not support vectored interrupts. It's safe to
|
|
|
+ say Y here.
|
|
|
+
|
|
|
+config CPU_MIPSR2_IRQ_EI
|
|
|
+ bool "External interrupt controller mode"
|
|
|
+ help
|
|
|
+ Extended interrupt mode takes advantage of an external interrupt
|
|
|
+ controller to allow fast dispatching from many possible interrupt
|
|
|
+ sources. Say N unless you know that external interrupt support is
|
|
|
+ required.
|
|
|
+
|
|
|
+config CPU_MIPSR2_SRS
|
|
|
+ bool "Make shadow set registers available for interrupt handlers"
|
|
|
+ depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
|
|
|
+ help
|
|
|
+ Allow the kernel to use shadow register sets for fast interrupts.
|
|
|
+ Interrupt handlers must be specially written to use shadow sets.
|
|
|
+ Say N unless you know that shadow register set upport is needed.
|
|
|
+endmenu
|
|
|
+
|
|
|
config CPU_HAS_SYNC
|
|
|
bool
|
|
|
depends on !CPU_R3000
|
|
|
default y
|
|
|
|
|
|
+#
|
|
|
+# Use the generic interrupt handling code in kernel/irq/:
|
|
|
+#
|
|
|
+config GENERIC_HARDIRQS
|
|
|
+ bool
|
|
|
+ default y
|
|
|
+
|
|
|
+config GENERIC_IRQ_PROBE
|
|
|
+ bool
|
|
|
+ default y
|
|
|
+
|
|
|
#
|
|
|
# - Highmem only makes sense for the 32-bit kernel.
|
|
|
# - The current highmem code will only work properly on physically indexed
|
|
@@ -1491,14 +1564,19 @@ config CPU_HAS_SYNC
|
|
|
# where it's known to be safe. This will not offer highmem on a few systems
|
|
|
# such as MIPS32 and MIPS64 CPUs which may have virtual and physically
|
|
|
# indexed CPUs but we're playing safe.
|
|
|
-# - We should not offer highmem for system of which we already know that they
|
|
|
-# don't have memory configurations that could gain from highmem support in
|
|
|
-# the kernel because they don't support configurations with RAM at physical
|
|
|
-# addresses > 0x20000000.
|
|
|
+# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
|
|
|
+# know they might have memory configurations that could make use of highmem
|
|
|
+# support.
|
|
|
#
|
|
|
config HIGHMEM
|
|
|
bool "High Memory Support"
|
|
|
- depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX)
|
|
|
+ depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
|
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+
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+config CPU_SUPPORTS_HIGHMEM
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|
|
+ bool
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+
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+config SYS_SUPPORTS_HIGHMEM
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|
+ bool
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|
|
|
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config ARCH_FLATMEM_ENABLE
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|
def_bool y
|
|
@@ -1508,7 +1586,7 @@ source "mm/Kconfig"
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|
|
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|
config SMP
|
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|
bool "Multi-Processing support"
|
|
|
- depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27
|
|
|
+ depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP
|
|
|
---help---
|
|
|
This enables support for systems with more than one CPU. If you have
|
|
|
a system with only one CPU, like most personal computers, say N. If
|
|
@@ -1543,14 +1621,7 @@ config NR_CPUS
|
|
|
This is purely to save memory - each supported CPU adds
|
|
|
approximately eight kilobytes to the kernel image.
|
|
|
|
|
|
-config PREEMPT
|
|
|
- bool "Preemptible Kernel"
|
|
|
- help
|
|
|
- This option reduces the latency of the kernel when reacting to
|
|
|
- real-time or interactive events by allowing a low priority process to
|
|
|
- be preempted even if it is in kernel mode executing a system call.
|
|
|
- This allows applications to run more reliably even when the system is
|
|
|
- under load.
|
|
|
+source "kernel/Kconfig.preempt"
|
|
|
|
|
|
config RTC_DS1742
|
|
|
bool "DS1742 BRAM/RTC support"
|
|
@@ -1566,14 +1637,16 @@ config MIPS_INSANE_LARGE
|
|
|
This will result in additional memory usage, so it is not
|
|
|
recommended for normal users.
|
|
|
|
|
|
+endmenu
|
|
|
+
|
|
|
config RWSEM_GENERIC_SPINLOCK
|
|
|
bool
|
|
|
default y
|
|
|
|
|
|
-endmenu
|
|
|
-
|
|
|
menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
|
|
|
|
|
|
+config HW_HAS_EISA
|
|
|
+ bool
|
|
|
config HW_HAS_PCI
|
|
|
bool
|
|
|
|
|
@@ -1607,7 +1680,7 @@ config ISA
|
|
|
|
|
|
config EISA
|
|
|
bool "EISA support"
|
|
|
- depends on SGI_IP22 || SNI_RM200_PCI
|
|
|
+ depends on HW_HAS_EISA
|
|
|
select ISA
|
|
|
---help---
|
|
|
The Extended Industry Standard Architecture (EISA) bus was
|
|
@@ -1641,12 +1714,6 @@ config MMU
|
|
|
bool
|
|
|
default y
|
|
|
|
|
|
-config MCA
|
|
|
- bool
|
|
|
-
|
|
|
-config SBUS
|
|
|
- bool
|
|
|
-
|
|
|
source "drivers/pcmcia/Kconfig"
|
|
|
|
|
|
source "drivers/pci/hotplug/Kconfig"
|
|
@@ -1659,7 +1726,6 @@ source "fs/Kconfig.binfmt"
|
|
|
|
|
|
config TRAD_SIGNALS
|
|
|
bool
|
|
|
- default y if 32BIT
|
|
|
|
|
|
config BUILD_ELF64
|
|
|
bool "Use 64-bit ELF format for building"
|
|
@@ -1678,7 +1744,7 @@ config BUILD_ELF64
|
|
|
|
|
|
config BINFMT_IRIX
|
|
|
bool "Include IRIX binary compatibility"
|
|
|
- depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN
|
|
|
+ depends on CPU_BIG_ENDIAN && 32BIT && BROKEN
|
|
|
|
|
|
config MIPS32_COMPAT
|
|
|
bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
|
|
@@ -1718,9 +1784,26 @@ config BINFMT_ELF32
|
|
|
bool
|
|
|
default y if MIPS32_O32 || MIPS32_N32
|
|
|
|
|
|
+config SECCOMP
|
|
|
+ bool "Enable seccomp to safely compute untrusted bytecode"
|
|
|
+ depends on PROC_FS && BROKEN
|
|
|
+ default y
|
|
|
+ help
|
|
|
+ This kernel feature is useful for number crunching applications
|
|
|
+ that may need to compute untrusted bytecode during their
|
|
|
+ execution. By using pipes or other transports made available to
|
|
|
+ the process as file descriptors supporting the read/write
|
|
|
+ syscalls, it's possible to isolate those applications in
|
|
|
+ their own address space using seccomp. Once seccomp is
|
|
|
+ enabled via /proc/<pid>/seccomp, it cannot be disabled
|
|
|
+ and the task is only allowed to execute a few safe syscalls
|
|
|
+ defined by each seccomp mode.
|
|
|
+
|
|
|
+ If unsure, say Y. Only embedded should say N here.
|
|
|
+
|
|
|
config PM
|
|
|
bool "Power Management support (EXPERIMENTAL)"
|
|
|
- depends on EXPERIMENTAL && MACH_AU1X00
|
|
|
+ depends on EXPERIMENTAL && SOC_AU1X00
|
|
|
|
|
|
endmenu
|
|
|
|
|
@@ -1730,6 +1813,8 @@ source "drivers/Kconfig"
|
|
|
|
|
|
source "fs/Kconfig"
|
|
|
|
|
|
+source "arch/mips/oprofile/Kconfig"
|
|
|
+
|
|
|
source "arch/mips/Kconfig.debug"
|
|
|
|
|
|
source "security/Kconfig"
|
|
@@ -1737,18 +1822,3 @@ source "security/Kconfig"
|
|
|
source "crypto/Kconfig"
|
|
|
|
|
|
source "lib/Kconfig"
|
|
|
-
|
|
|
-#
|
|
|
-# Use the generic interrupt handling code in kernel/irq/:
|
|
|
-#
|
|
|
-config GENERIC_HARDIRQS
|
|
|
- bool
|
|
|
- default y
|
|
|
-
|
|
|
-config GENERIC_IRQ_PROBE
|
|
|
- bool
|
|
|
- default y
|
|
|
-
|
|
|
-config ISA_DMA_API
|
|
|
- bool
|
|
|
- default y
|