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@@ -233,6 +233,24 @@ static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
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core_writel(priv, reg, CORE_EEE_EN_CTRL);
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}
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+static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
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+{
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+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
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+ u32 reg;
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+
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+ if (!enable)
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+ return;
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+
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+ reg = reg_readl(priv, REG_SPHY_CNTRL);
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+ reg |= PHY_RESET;
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+ reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS);
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+ reg_writel(priv, reg, REG_SPHY_CNTRL);
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+ udelay(21);
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+ reg = reg_readl(priv, REG_SPHY_CNTRL);
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+ reg &= ~PHY_RESET;
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+ reg_writel(priv, reg, REG_SPHY_CNTRL);
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+}
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+
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static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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struct phy_device *phy)
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{
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@@ -771,7 +789,6 @@ static int bcm_sf2_sw_resume(struct dsa_switch *ds)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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unsigned int port;
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- u32 reg;
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int ret;
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ret = bcm_sf2_sw_rst(priv);
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@@ -780,17 +797,8 @@ static int bcm_sf2_sw_resume(struct dsa_switch *ds)
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return ret;
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}
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- /* Reinitialize the single GPHY */
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- if (priv->hw_params.num_gphy == 1) {
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- reg = reg_readl(priv, REG_SPHY_CNTRL);
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- reg |= PHY_RESET;
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- reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS);
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- reg_writel(priv, reg, REG_SPHY_CNTRL);
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- udelay(21);
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- reg = reg_readl(priv, REG_SPHY_CNTRL);
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- reg &= ~PHY_RESET;
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- reg_writel(priv, reg, REG_SPHY_CNTRL);
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- }
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+ if (priv->hw_params.num_gphy == 1)
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+ bcm_sf2_gphy_enable_set(ds, true);
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for (port = 0; port < DSA_MAX_PORTS; port++) {
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if ((1 << port) & ds->phys_port_mask)
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