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@@ -372,26 +372,9 @@ static bool intel_pstate_get_ppc_enable_status(void)
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return acpi_ppc;
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}
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-/*
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- * The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and
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- * in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and
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- * max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state
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- * ratio, out of it only high 8 bits are used. For example 0x1700 is setting
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- * target ratio 0x17. The _PSS control value stores in a format which can be
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- * directly written to PERF_CTL MSR. But in intel_pstate driver this shift
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- * occurs during write to PERF_CTL (E.g. for cores core_set_pstate()).
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- * This function converts the _PSS control value to intel pstate driver format
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- * for comparison and assignment.
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- */
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-static int convert_to_native_pstate_format(struct cpudata *cpu, int index)
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-{
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- return cpu->acpi_perf_data.states[index].control >> 8;
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-}
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-
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static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
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{
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struct cpudata *cpu;
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- int turbo_pss_ctl;
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int ret;
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int i;
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@@ -441,11 +424,10 @@ static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
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* max frequency, which will cause a reduced performance as
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* this driver uses real max turbo frequency as the max
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* frequency. So correct this frequency in _PSS table to
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- * correct max turbo frequency based on the turbo ratio.
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+ * correct max turbo frequency based on the turbo state.
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* Also need to convert to MHz as _PSS freq is in MHz.
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*/
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- turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0);
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- if (turbo_pss_ctl > cpu->pstate.max_pstate)
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+ if (!limits->turbo_disabled)
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cpu->acpi_perf_data.states[0].core_frequency =
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policy->cpuinfo.max_freq / 1000;
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cpu->valid_pss_table = true;
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