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@@ -116,7 +116,7 @@ static const struct gma_limit_t cdv_intel_limits[] = {
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.p1 = {.min = 1, .max = 10},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
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.find_pll = cdv_intel_find_dp_pll,
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- }
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+ }
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};
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#define _wait_for(COND, MS, W) ({ \
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@@ -245,7 +245,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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/* We don't know what the other fields of these regs are, so
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* leave them in place.
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*/
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- /*
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+ /*
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* The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
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* for the pipe A/B. Display spec 1.06 has wrong definition.
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* Correct definition is like below:
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@@ -256,7 +256,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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*
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* if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
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*
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- */
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+ */
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ret = cdv_sb_read(dev, ref_sfr, &ref_value);
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if (ret)
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return ret;
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@@ -646,7 +646,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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* for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
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* it will be 27MHz. From the VBIOS code it seems that the pipe A choose
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* 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
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- */
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+ */
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if (pipe == 0)
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refclk = 27000;
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else
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@@ -659,7 +659,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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drm_mode_debug_printmodeline(adjusted_mode);
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-
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+
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limit = gma_crtc->clock_funcs->limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
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@@ -721,7 +721,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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pipeconf |= PIPE_6BPC;
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} else
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pipeconf |= PIPE_8BPC;
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-
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+
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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@@ -974,7 +974,6 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
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const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
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.dpms = gma_crtc_dpms,
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- .mode_fixup = gma_crtc_mode_fixup,
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.mode_set = cdv_intel_crtc_mode_set,
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.mode_set_base = gma_pipe_set_base,
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.prepare = gma_crtc_prepare,
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