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ARM: tegra: remove ifdef in the tegra_resume

The ifdef was originally added with the intent that the runtime SoC
detection code, and code to support SoCs other than Tegra20, was only
included if the kernel supported SoCs other than Tegra20. However,
the condition was somewhat backwards and did not achieve this goal.
Simply remove the ifdef to solve this, rather than creating a much more
complex version.

We also fix a typo that caused a build error due to cpu_to_csr_req being
undefined.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren: rewrote commit description]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo 12 年之前
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共有 1 个文件被更改,包括 1 次插入3 次删除
  1. 1 3
      arch/arm/mach-tegra/reset-handler.S

+ 1 - 3
arch/arm/mach-tegra/reset-handler.S

@@ -54,12 +54,11 @@ ENTRY(tegra_resume)
 	bne	cpu_resume			@ no
 	bne	cpu_resume			@ no
 no_cpu0_chk:
 no_cpu0_chk:
 
 
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
 	/* Are we on Tegra20? */
 	/* Are we on Tegra20? */
 	cmp	r6, #TEGRA20
 	cmp	r6, #TEGRA20
 	beq	1f				@ Yes
 	beq	1f				@ Yes
 	/* Clear the flow controller flags for this CPU. */
 	/* Clear the flow controller flags for this CPU. */
-	cpu_to_csr_req r1, r0
+	cpu_to_csr_reg r1, r0
 	mov32	r2, TEGRA_FLOW_CTRL_BASE
 	mov32	r2, TEGRA_FLOW_CTRL_BASE
 	ldr	r1, [r2, r1]
 	ldr	r1, [r2, r1]
 	/* Clear event & intr flag */
 	/* Clear event & intr flag */
@@ -70,7 +69,6 @@ no_cpu0_chk:
 	bic	r1, r1, r0
 	bic	r1, r1, r0
 	str	r1, [r2]
 	str	r1, [r2]
 1:
 1:
-#endif
 
 
 	check_cpu_part_num 0xc09, r8, r9
 	check_cpu_part_num 0xc09, r8, r9
 	bne	not_ca9
 	bne	not_ca9