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@@ -69,21 +69,35 @@
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* samples will be written to STX properly.
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*/
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#ifdef __BIG_ENDIAN
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-#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
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- SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
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- SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
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+#define FSLSSI_I2S_FORMATS \
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+ (SNDRV_PCM_FMTBIT_S8 | \
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+ SNDRV_PCM_FMTBIT_S16_BE | \
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+ SNDRV_PCM_FMTBIT_S18_3BE | \
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+ SNDRV_PCM_FMTBIT_S20_3BE | \
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+ SNDRV_PCM_FMTBIT_S24_3BE | \
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+ SNDRV_PCM_FMTBIT_S24_BE)
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#else
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-#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
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- SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
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- SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
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+#define FSLSSI_I2S_FORMATS \
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+ (SNDRV_PCM_FMTBIT_S8 | \
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+ SNDRV_PCM_FMTBIT_S16_LE | \
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+ SNDRV_PCM_FMTBIT_S18_3LE | \
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+ SNDRV_PCM_FMTBIT_S20_3LE | \
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+ SNDRV_PCM_FMTBIT_S24_3LE | \
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+ SNDRV_PCM_FMTBIT_S24_LE)
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#endif
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-#define FSLSSI_SIER_DBG_RX_FLAGS (SSI_SIER_RFF0_EN | \
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- SSI_SIER_RLS_EN | SSI_SIER_RFS_EN | \
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- SSI_SIER_ROE0_EN | SSI_SIER_RFRC_EN)
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-#define FSLSSI_SIER_DBG_TX_FLAGS (SSI_SIER_TFE0_EN | \
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- SSI_SIER_TLS_EN | SSI_SIER_TFS_EN | \
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- SSI_SIER_TUE0_EN | SSI_SIER_TFRC_EN)
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+#define FSLSSI_SIER_DBG_RX_FLAGS \
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+ (SSI_SIER_RFF0_EN | \
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+ SSI_SIER_RLS_EN | \
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+ SSI_SIER_RFS_EN | \
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+ SSI_SIER_ROE0_EN | \
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+ SSI_SIER_RFRC_EN)
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+#define FSLSSI_SIER_DBG_TX_FLAGS \
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+ (SSI_SIER_TFE0_EN | \
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+ SSI_SIER_TLS_EN | \
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+ SSI_SIER_TFS_EN | \
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+ SSI_SIER_TUE0_EN | \
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+ SSI_SIER_TFRC_EN)
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enum fsl_ssi_type {
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FSL_SSI_MCP8610,
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@@ -291,8 +305,8 @@ static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
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.imx = false,
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.offline_config = true,
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.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
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- SSI_SISR_ROE0 | SSI_SISR_ROE1 |
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- SSI_SISR_TUE0 | SSI_SISR_TUE1,
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+ SSI_SISR_ROE0 | SSI_SISR_ROE1 |
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+ SSI_SISR_TUE0 | SSI_SISR_TUE1,
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};
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static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
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@@ -306,15 +320,15 @@ static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
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.imx = true,
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.offline_config = true,
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.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
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- SSI_SISR_ROE0 | SSI_SISR_ROE1 |
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- SSI_SISR_TUE0 | SSI_SISR_TUE1,
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+ SSI_SISR_ROE0 | SSI_SISR_ROE1 |
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+ SSI_SISR_TUE0 | SSI_SISR_TUE1,
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};
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static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
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.imx = true,
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.offline_config = false,
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.sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
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- SSI_SISR_TUE0 | SSI_SISR_TUE1,
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+ SSI_SISR_TUE0 | SSI_SISR_TUE1,
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};
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static const struct of_device_id fsl_ssi_ids[] = {
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@@ -376,21 +390,21 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable)
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if (enable) {
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regmap_update_bits(regs, REG_SSI_SIER,
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- vals->rx.sier | vals->tx.sier,
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- vals->rx.sier | vals->tx.sier);
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+ vals->rx.sier | vals->tx.sier,
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+ vals->rx.sier | vals->tx.sier);
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regmap_update_bits(regs, REG_SSI_SRCR,
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- vals->rx.srcr | vals->tx.srcr,
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- vals->rx.srcr | vals->tx.srcr);
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+ vals->rx.srcr | vals->tx.srcr,
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+ vals->rx.srcr | vals->tx.srcr);
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regmap_update_bits(regs, REG_SSI_STCR,
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- vals->rx.stcr | vals->tx.stcr,
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- vals->rx.stcr | vals->tx.stcr);
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+ vals->rx.stcr | vals->tx.stcr,
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+ vals->rx.stcr | vals->tx.stcr);
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} else {
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regmap_update_bits(regs, REG_SSI_SRCR,
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- vals->rx.srcr | vals->tx.srcr, 0);
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+ vals->rx.srcr | vals->tx.srcr, 0);
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regmap_update_bits(regs, REG_SSI_STCR,
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- vals->rx.stcr | vals->tx.stcr, 0);
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+ vals->rx.stcr | vals->tx.stcr, 0);
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regmap_update_bits(regs, REG_SSI_SIER,
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- vals->rx.sier | vals->tx.sier, 0);
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+ vals->rx.sier | vals->tx.sier, 0);
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}
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}
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@@ -401,10 +415,10 @@ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx)
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{
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if (is_rx) {
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regmap_update_bits(ssi->regs, REG_SSI_SOR,
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- SSI_SOR_RX_CLR, SSI_SOR_RX_CLR);
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+ SSI_SOR_RX_CLR, SSI_SOR_RX_CLR);
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} else {
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regmap_update_bits(ssi->regs, REG_SSI_SOR,
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- SSI_SOR_TX_CLR, SSI_SOR_TX_CLR);
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+ SSI_SOR_TX_CLR, SSI_SOR_TX_CLR);
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}
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}
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@@ -432,7 +446,7 @@ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx)
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* Enable or disable SSI configuration.
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*/
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static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
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- struct fsl_ssi_reg_val *vals)
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+ struct fsl_ssi_reg_val *vals)
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{
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struct regmap *regs = ssi->regs;
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struct fsl_ssi_reg_val *avals;
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@@ -442,8 +456,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
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regmap_read(regs, REG_SSI_SCR, &scr_val);
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- nr_active_streams = !!(scr_val & SSI_SCR_TE) +
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- !!(scr_val & SSI_SCR_RE);
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+ nr_active_streams = !!(scr_val & SSI_SCR_TE) + !!(scr_val & SSI_SCR_RE);
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if (nr_active_streams - 1 > 0)
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keep_active = 1;
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@@ -462,7 +475,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
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* both streams, and get safe bits to disable current stream
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*/
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u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
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- keep_active);
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+ keep_active);
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/* Safely disable SCR register for the stream */
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regmap_update_bits(regs, REG_SSI_SCR, scr, 0);
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}
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@@ -474,8 +487,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
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* 2) Disable all remaining bits of both streams when last stream ends
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*/
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if (ssi->soc->offline_config) {
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- if ((enable && !nr_active_streams) ||
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- (!enable && !keep_active))
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+ if ((enable && !nr_active_streams) || (!enable && !keep_active))
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fsl_ssi_rxtx_config(ssi, enable);
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goto config_done;
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@@ -498,11 +510,11 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
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* both streams, and get safe bits to disable current stream
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*/
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sier = fsl_ssi_disable_val(vals->sier, avals->sier,
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- keep_active);
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+ keep_active);
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srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
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- keep_active);
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+ keep_active);
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stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
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- keep_active);
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+ keep_active);
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/* Safely disable other control registers for the stream */
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regmap_update_bits(regs, REG_SSI_SRCR, srcr, 0);
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@@ -525,7 +537,7 @@ config_done:
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/* Enable SSI first to send TX DMA request */
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regmap_update_bits(regs, REG_SSI_SCR,
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- SSI_SCR_SSIEN, SSI_SCR_SSIEN);
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+ SSI_SCR_SSIEN, SSI_SCR_SSIEN);
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/* Busy wait until TX FIFO not empty -- DMA working */
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for (i = 0; i < max_loop; i++) {
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@@ -544,7 +556,6 @@ config_done:
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}
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}
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-
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static void fsl_ssi_rx_config(struct fsl_ssi *ssi, bool enable)
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{
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fsl_ssi_config(ssi, enable, &ssi->rxtx_reg_val.rx);
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@@ -615,19 +626,16 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
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struct regmap *regs = ssi->regs;
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/* Setup the clock control register */
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- regmap_write(regs, REG_SSI_STCCR,
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- SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
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- regmap_write(regs, REG_SSI_SRCCR,
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- SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
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+ regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
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+ regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
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/* Enable AC97 mode and startup the SSI */
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- regmap_write(regs, REG_SSI_SACNT,
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- SSI_SACNT_AC97EN | SSI_SACNT_FV);
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+ regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
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/* AC97 has to communicate with codec before starting a stream */
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regmap_update_bits(regs, REG_SSI_SCR,
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- SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
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- SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
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+ SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
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+ SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
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regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
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}
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@@ -651,19 +659,18 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
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*/
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if (ssi->use_dual_fifo)
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snd_pcm_hw_constraint_step(substream->runtime, 0,
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- SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
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+ SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
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return 0;
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}
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static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
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- struct snd_soc_dai *dai)
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+ struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
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clk_disable_unprepare(ssi->clk);
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-
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}
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/**
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@@ -676,8 +683,8 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
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* (In 2-channel I2S Master mode, slot_width is fixed 32)
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*/
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static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
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- struct snd_soc_dai *cpu_dai,
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- struct snd_pcm_hw_params *hw_params)
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+ struct snd_soc_dai *cpu_dai,
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+ struct snd_pcm_hw_params *hw_params)
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{
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struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
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struct regmap *regs = ssi->regs;
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@@ -764,8 +771,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
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stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
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(psr ? SSI_SxCCR_PSR : 0);
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- mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 |
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- SSI_SxCCR_PSR;
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+ mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
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regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr);
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@@ -795,7 +801,8 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
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* fsl_ssi_set_bclk() if SSI is the DAI clock master.
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*/
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static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
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- struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
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+ struct snd_pcm_hw_params *hw_params,
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+ struct snd_soc_dai *cpu_dai)
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{
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struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
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struct regmap *regs = ssi->regs;
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@@ -837,36 +844,33 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
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u8 i2smode;
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/* Normal + Network mode to send 16-bit data in 32-bit frames */
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if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
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- i2smode = SSI_SCR_I2S_MODE_NORMAL |
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- SSI_SCR_NET;
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+ i2smode = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
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else
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i2smode = ssi->i2s_mode;
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regmap_update_bits(regs, REG_SSI_SCR,
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- SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK,
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- channels == 1 ? 0 : i2smode);
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+ SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK,
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+ channels == 1 ? 0 : i2smode);
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}
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/* In synchronous mode, the SSI uses STCCR for capture */
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if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
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ssi->cpu_dai_drv.symmetric_rates)
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- regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK,
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- wl);
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+ regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK, wl);
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else
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- regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK,
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- wl);
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+ regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK, wl);
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return 0;
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}
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static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
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- struct snd_soc_dai *cpu_dai)
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+ struct snd_soc_dai *cpu_dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
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if (fsl_ssi_is_i2s_master(ssi) &&
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- ssi->baudclk_streams & BIT(substream->stream)) {
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+ ssi->baudclk_streams & BIT(substream->stream)) {
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clk_disable_unprepare(ssi->baudclk);
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ssi->baudclk_streams &= ~BIT(substream->stream);
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}
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@@ -896,8 +900,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
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scr |= SSI_SCR_SYNC_TX_FS;
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mask = SSI_STCR_TXBIT0 | SSI_STCR_TFDIR | SSI_STCR_TXDIR |
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- SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL |
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- SSI_STCR_TEFS;
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|
|
+ SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL | SSI_STCR_TEFS;
|
|
|
regmap_read(regs, REG_SSI_STCR, &stcr);
|
|
|
regmap_read(regs, REG_SSI_SRCR, &srcr);
|
|
|
stcr &= ~mask;
|
|
@@ -908,11 +911,9 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
regmap_update_bits(regs, REG_SSI_STCCR,
|
|
|
- SSI_SxCCR_DC_MASK,
|
|
|
- SSI_SxCCR_DC(2));
|
|
|
+ SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2));
|
|
|
regmap_update_bits(regs, REG_SSI_SRCCR,
|
|
|
- SSI_SxCCR_DC_MASK,
|
|
|
- SSI_SxCCR_DC(2));
|
|
|
+ SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2));
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
@@ -927,7 +928,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
|
|
|
|
|
|
/* Data on rising edge of bclk, frame low, 1clk before data */
|
|
|
strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP |
|
|
|
- SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
|
|
|
+ SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
|
|
|
break;
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
/* Data on rising edge of bclk, frame high */
|
|
@@ -936,12 +937,11 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
/* Data on rising edge of bclk, frame high, 1clk before data */
|
|
|
strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP |
|
|
|
- SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
|
|
|
+ SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
|
|
|
break;
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
/* Data on rising edge of bclk, frame high */
|
|
|
- strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP |
|
|
|
- SSI_STCR_TXBIT0;
|
|
|
+ strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TXBIT0;
|
|
|
break;
|
|
|
case SND_SOC_DAIFMT_AC97:
|
|
|
/* Data on falling edge of bclk, frame high, 1clk before data */
|
|
@@ -1012,23 +1012,22 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
|
|
|
wm = ssi->fifo_watermark;
|
|
|
|
|
|
regmap_write(regs, REG_SSI_SFCSR,
|
|
|
- SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
|
|
|
- SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
|
|
|
+ SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
|
|
|
+ SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
|
|
|
|
|
|
if (ssi->use_dual_fifo) {
|
|
|
- regmap_update_bits(regs, REG_SSI_SRCR, SSI_SRCR_RFEN1,
|
|
|
- SSI_SRCR_RFEN1);
|
|
|
- regmap_update_bits(regs, REG_SSI_STCR, SSI_STCR_TFEN1,
|
|
|
- SSI_STCR_TFEN1);
|
|
|
- regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_TCH_EN,
|
|
|
- SSI_SCR_TCH_EN);
|
|
|
+ regmap_update_bits(regs, REG_SSI_SRCR,
|
|
|
+ SSI_SRCR_RFEN1, SSI_SRCR_RFEN1);
|
|
|
+ regmap_update_bits(regs, REG_SSI_STCR,
|
|
|
+ SSI_STCR_TFEN1, SSI_STCR_TFEN1);
|
|
|
+ regmap_update_bits(regs, REG_SSI_SCR,
|
|
|
+ SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
|
|
|
}
|
|
|
|
|
|
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
|
|
|
fsl_ssi_setup_ac97(ssi);
|
|
|
|
|
|
return 0;
|
|
|
-
|
|
|
}
|
|
|
|
|
|
/**
|
|
@@ -1049,7 +1048,7 @@ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
|
|
* Set TDM slot number and slot width
|
|
|
*/
|
|
|
static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
|
|
|
- u32 rx_mask, int slots, int slot_width)
|
|
|
+ u32 rx_mask, int slots, int slot_width)
|
|
|
{
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
|
|
|
struct regmap *regs = ssi->regs;
|
|
@@ -1069,17 +1068,16 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
- regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_DC_MASK,
|
|
|
- SSI_SxCCR_DC(slots));
|
|
|
- regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_DC_MASK,
|
|
|
- SSI_SxCCR_DC(slots));
|
|
|
+ regmap_update_bits(regs, REG_SSI_STCCR,
|
|
|
+ SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
|
|
|
+ regmap_update_bits(regs, REG_SSI_SRCCR,
|
|
|
+ SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
|
|
|
|
|
|
/* Save SSIEN bit of the SCR register */
|
|
|
regmap_read(regs, REG_SSI_SCR, &val);
|
|
|
val &= SSI_SCR_SSIEN;
|
|
|
/* Temporarily enable SSI to allow SxMSKs to be configurable */
|
|
|
- regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN,
|
|
|
- SSI_SCR_SSIEN);
|
|
|
+ regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
|
|
|
|
|
|
regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
|
|
|
regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
|
|
@@ -1153,13 +1151,13 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
|
|
|
}
|
|
|
|
|
|
static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
|
|
|
- .startup = fsl_ssi_startup,
|
|
|
- .shutdown = fsl_ssi_shutdown,
|
|
|
- .hw_params = fsl_ssi_hw_params,
|
|
|
- .hw_free = fsl_ssi_hw_free,
|
|
|
- .set_fmt = fsl_ssi_set_dai_fmt,
|
|
|
- .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
|
|
|
- .trigger = fsl_ssi_trigger,
|
|
|
+ .startup = fsl_ssi_startup,
|
|
|
+ .shutdown = fsl_ssi_shutdown,
|
|
|
+ .hw_params = fsl_ssi_hw_params,
|
|
|
+ .hw_free = fsl_ssi_hw_free,
|
|
|
+ .set_fmt = fsl_ssi_set_dai_fmt,
|
|
|
+ .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
|
|
|
+ .trigger = fsl_ssi_trigger,
|
|
|
};
|
|
|
|
|
|
static struct snd_soc_dai_driver fsl_ssi_dai_template = {
|
|
@@ -1182,7 +1180,7 @@ static struct snd_soc_dai_driver fsl_ssi_dai_template = {
|
|
|
};
|
|
|
|
|
|
static const struct snd_soc_component_driver fsl_ssi_component = {
|
|
|
- .name = "fsl-ssi",
|
|
|
+ .name = "fsl-ssi",
|
|
|
};
|
|
|
|
|
|
static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
|
|
@@ -1206,11 +1204,10 @@ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
|
|
|
.ops = &fsl_ssi_dai_ops,
|
|
|
};
|
|
|
|
|
|
-
|
|
|
static struct fsl_ssi *fsl_ac97_data;
|
|
|
|
|
|
static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
|
|
- unsigned short val)
|
|
|
+ unsigned short val)
|
|
|
{
|
|
|
struct regmap *regs = fsl_ac97_data->regs;
|
|
|
unsigned int lreg;
|
|
@@ -1235,8 +1232,8 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
|
|
lval = val << 4;
|
|
|
regmap_write(regs, REG_SSI_SACDAT, lval);
|
|
|
|
|
|
- regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK,
|
|
|
- SSI_SACNT_WR);
|
|
|
+ regmap_update_bits(regs, REG_SSI_SACNT,
|
|
|
+ SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
|
|
|
udelay(100);
|
|
|
|
|
|
clk_disable_unprepare(fsl_ac97_data->clk);
|
|
@@ -1246,10 +1243,9 @@ ret_unlock:
|
|
|
}
|
|
|
|
|
|
static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
|
|
|
- unsigned short reg)
|
|
|
+ unsigned short reg)
|
|
|
{
|
|
|
struct regmap *regs = fsl_ac97_data->regs;
|
|
|
-
|
|
|
unsigned short val = 0;
|
|
|
u32 reg_val;
|
|
|
unsigned int lreg;
|
|
@@ -1259,15 +1255,14 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
|
|
|
|
|
|
ret = clk_prepare_enable(fsl_ac97_data->clk);
|
|
|
if (ret) {
|
|
|
- pr_err("ac97 read clk_prepare_enable failed: %d\n",
|
|
|
- ret);
|
|
|
+ pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
|
|
|
goto ret_unlock;
|
|
|
}
|
|
|
|
|
|
lreg = (reg & 0x7f) << 12;
|
|
|
regmap_write(regs, REG_SSI_SACADD, lreg);
|
|
|
- regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK,
|
|
|
- SSI_SACNT_RD);
|
|
|
+ regmap_update_bits(regs, REG_SSI_SACNT,
|
|
|
+ SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
@@ -1282,8 +1277,8 @@ ret_unlock:
|
|
|
}
|
|
|
|
|
|
static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
|
|
|
- .read = fsl_ssi_ac97_read,
|
|
|
- .write = fsl_ssi_ac97_write,
|
|
|
+ .read = fsl_ssi_ac97_read,
|
|
|
+ .write = fsl_ssi_ac97_write,
|
|
|
};
|
|
|
|
|
|
/**
|
|
@@ -1298,7 +1293,7 @@ static void make_lowercase(char *s)
|
|
|
}
|
|
|
|
|
|
static int fsl_ssi_imx_probe(struct platform_device *pdev,
|
|
|
- struct fsl_ssi *ssi, void __iomem *iomem)
|
|
|
+ struct fsl_ssi *ssi, void __iomem *iomem)
|
|
|
{
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
struct device *dev = &pdev->dev;
|
|
@@ -1370,14 +1365,13 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
|
|
|
return 0;
|
|
|
|
|
|
error_pcm:
|
|
|
-
|
|
|
if (!ssi->has_ipg_clk_name)
|
|
|
clk_disable_unprepare(ssi->clk);
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-static void fsl_ssi_imx_clean(struct platform_device *pdev,
|
|
|
- struct fsl_ssi *ssi)
|
|
|
+static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
|
|
|
{
|
|
|
if (!ssi->use_dma)
|
|
|
imx_pcm_fiq_exit(pdev);
|
|
@@ -1422,8 +1416,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|
|
|
|
|
if (fsl_ssi_is_ac97(ssi)) {
|
|
|
memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
|
|
|
- sizeof(fsl_ssi_ac97_dai));
|
|
|
-
|
|
|
+ sizeof(fsl_ssi_ac97_dai));
|
|
|
fsl_ac97_data = ssi;
|
|
|
} else {
|
|
|
memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
|
|
@@ -1582,8 +1575,8 @@ done:
|
|
|
goto error_sound_card;
|
|
|
}
|
|
|
|
|
|
- ssi->pdev = platform_device_register_data(NULL,
|
|
|
- "ac97-codec", ssi_idx, NULL, 0);
|
|
|
+ ssi->pdev = platform_device_register_data(NULL, "ac97-codec",
|
|
|
+ ssi_idx, NULL, 0);
|
|
|
if (IS_ERR(ssi->pdev)) {
|
|
|
ret = PTR_ERR(ssi->pdev);
|
|
|
dev_err(dev,
|
|
@@ -1597,11 +1590,9 @@ done:
|
|
|
|
|
|
error_sound_card:
|
|
|
fsl_ssi_debugfs_remove(&ssi->dbg_stats);
|
|
|
-
|
|
|
error_asoc_register:
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
|
|
snd_soc_set_ac97_ops(NULL);
|
|
|
-
|
|
|
error_ac97_ops:
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
|
|
mutex_destroy(&ssi->ac97_reg_lock);
|
|
@@ -1655,9 +1646,9 @@ static int fsl_ssi_resume(struct device *dev)
|
|
|
regcache_cache_only(regs, false);
|
|
|
|
|
|
regmap_update_bits(regs, REG_SSI_SFCSR,
|
|
|
- SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
|
|
|
- SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
|
|
|
- ssi->regcache_sfcsr);
|
|
|
+ SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
|
|
|
+ SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
|
|
|
+ ssi->regcache_sfcsr);
|
|
|
regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
|
|
|
|
|
|
return regcache_sync(regs);
|