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@@ -7602,7 +7602,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, base, offset;
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- int pipe = crtc->pipe, plane = crtc->plane;
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+ int pipe = crtc->pipe;
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int fourcc, pixel_format;
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int aligned_height;
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struct drm_framebuffer *fb;
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@@ -7613,7 +7613,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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return;
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}
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- val = I915_READ(DSPCNTR(plane));
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+ val = I915_READ(DSPCNTR(pipe));
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if (INTEL_INFO(dev)->gen >= 4)
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if (val & DISPPLANE_TILED)
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@@ -7624,14 +7624,14 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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fb->pixel_format = fourcc;
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fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
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- base = I915_READ(DSPSURF(plane)) & 0xfffff000;
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+ base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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- offset = I915_READ(DSPOFFSET(plane));
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+ offset = I915_READ(DSPOFFSET(pipe));
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} else {
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if (plane_config->tiling)
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- offset = I915_READ(DSPTILEOFF(plane));
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+ offset = I915_READ(DSPTILEOFF(pipe));
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else
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- offset = I915_READ(DSPLINOFF(plane));
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+ offset = I915_READ(DSPLINOFF(pipe));
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}
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plane_config->base = base;
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@@ -7647,8 +7647,8 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
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- DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
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- pipe, plane, fb->width, fb->height, fb->bits_per_pixel,
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+ DRM_DEBUG_KMS("pipe %d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
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+ pipe, fb->width, fb->height, fb->bits_per_pixel,
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base, fb->pitches[0], plane_config->size);
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crtc->base.primary->fb = fb;
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