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@@ -479,6 +479,12 @@ void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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+ if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
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+ ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
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+ offset, offset + sizeof(value), ar_pci->mem_len);
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+ return;
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+ }
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+
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
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@@ -496,6 +502,12 @@ u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
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u32 val;
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int ret;
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+ if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
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+ ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
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+ offset, offset + sizeof(val), ar_pci->mem_len);
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+ return 0;
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+ }
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+
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
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@@ -2679,6 +2691,7 @@ static int ath10k_pci_claim(struct ath10k *ar)
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pci_set_master(pdev);
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/* Arrange for access to Target SoC registers. */
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+ ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
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ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
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if (!ar_pci->mem) {
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ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
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