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@@ -77,7 +77,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
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enum amdgpu_interrupt_state state)
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{
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struct amdgpu_vmhub *hub;
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- u32 tmp, reg, bits, i;
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+ u32 tmp, reg, bits, i, j;
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bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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@@ -89,43 +89,26 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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- /* MM HUB */
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- hub = &adev->vmhub[AMDGPU_MMHUB];
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- for (i = 0; i< 16; i++) {
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- reg = hub->vm_context0_cntl + i;
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- tmp = RREG32(reg);
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- tmp &= ~bits;
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- WREG32(reg, tmp);
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- }
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-
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- /* GFX HUB */
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- hub = &adev->vmhub[AMDGPU_GFXHUB];
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- for (i = 0; i < 16; i++) {
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- reg = hub->vm_context0_cntl + i;
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- tmp = RREG32(reg);
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- tmp &= ~bits;
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- WREG32(reg, tmp);
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+ for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
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+ hub = &adev->vmhub[j];
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+ for (i = 0; i < 16; i++) {
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+ reg = hub->vm_context0_cntl + i;
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+ tmp = RREG32(reg);
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+ tmp &= ~bits;
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+ WREG32(reg, tmp);
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+ }
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}
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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- /* MM HUB */
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- hub = &adev->vmhub[AMDGPU_MMHUB];
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- for (i = 0; i< 16; i++) {
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- reg = hub->vm_context0_cntl + i;
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- tmp = RREG32(reg);
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- tmp |= bits;
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- WREG32(reg, tmp);
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+ for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
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+ hub = &adev->vmhub[j];
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+ for (i = 0; i < 16; i++) {
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+ reg = hub->vm_context0_cntl + i;
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+ tmp = RREG32(reg);
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+ tmp |= bits;
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+ WREG32(reg, tmp);
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+ }
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}
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-
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- /* GFX HUB */
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- hub = &adev->vmhub[AMDGPU_GFXHUB];
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- for (i = 0; i < 16; i++) {
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- reg = hub->vm_context0_cntl + i;
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- tmp = RREG32(reg);
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- tmp |= bits;
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- WREG32(reg, tmp);
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- }
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- break;
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default:
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break;
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}
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