|
@@ -909,7 +909,7 @@
|
|
|
#clock-cells = <1>;
|
|
|
clock-output-names = "main", "pll0", "pll1", "pll3",
|
|
|
"lb", "qspi", "sdh", "sd0", "z",
|
|
|
- "rcan";
|
|
|
+ "rcan", "adsp";
|
|
|
};
|
|
|
|
|
|
/* Variable factor clocks */
|
|
@@ -1164,13 +1164,16 @@
|
|
|
mstp5_clks: mstp5_clks@e6150144 {
|
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
|
|
- clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
|
|
|
+ clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
|
|
|
+ <&extal_clk>, <&p_clk>;
|
|
|
#clock-cells = <1>;
|
|
|
clock-indices = <
|
|
|
R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
|
|
|
- R8A7791_CLK_THERMAL R8A7791_CLK_PWM
|
|
|
+ R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
|
|
|
+ R8A7791_CLK_PWM
|
|
|
>;
|
|
|
- clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
|
|
|
+ clock-output-names = "audmac0", "audmac1", "adsp_mod",
|
|
|
+ "thermal", "pwm";
|
|
|
};
|
|
|
mstp7_clks: mstp7_clks@e615014c {
|
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|