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@@ -17,6 +17,7 @@
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#include <linux/gpio.h>
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#include <linux/gpio-pxa.h>
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#include <linux/init.h>
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+#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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@@ -27,8 +28,6 @@
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#include <linux/syscore_ops.h>
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#include <linux/slab.h>
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-#include <mach/irqs.h>
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-
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/*
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* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
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* one set of registers. The register offsets are organized below:
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@@ -629,19 +628,18 @@ static int pxa_gpio_probe(struct platform_device *pdev)
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}
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if (!use_of) {
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-#ifdef CONFIG_ARCH_PXA
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- irq = gpio_to_irq(0);
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- irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
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- handle_edge_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
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-
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- irq = gpio_to_irq(1);
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- irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
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- handle_edge_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
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-#endif
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+ if (irq0 > 0) {
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+ irq = gpio_to_irq(0);
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+ irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
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+ handle_edge_irq);
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+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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+ }
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+ if (irq1 > 0) {
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+ irq = gpio_to_irq(1);
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+ irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
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+ handle_edge_irq);
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+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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+ }
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for (irq = gpio_to_irq(gpio_offset);
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irq <= gpio_to_irq(pxa_last_gpio); irq++) {
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@@ -649,13 +647,13 @@ static int pxa_gpio_probe(struct platform_device *pdev)
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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- } else {
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- if (irq0 > 0)
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- irq_set_chained_handler(irq0, pxa_gpio_demux_handler);
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- if (irq1 > 0)
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- irq_set_chained_handler(irq1, pxa_gpio_demux_handler);
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}
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+ if (irq0 > 0)
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+ irq_set_chained_handler(irq0, pxa_gpio_demux_handler);
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+ if (irq1 > 0)
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+ irq_set_chained_handler(irq1, pxa_gpio_demux_handler);
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+
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irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
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return 0;
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}
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