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@@ -78,13 +78,6 @@
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typedef unsigned char uchar;
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-#ifndef TRUE
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-#define TRUE (1)
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-#endif
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-#ifndef FALSE
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-#define FALSE (0)
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-#endif
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-
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#define ERR (-1)
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#define UW_ERR (uint)(0xFFFF)
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#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
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@@ -556,7 +549,7 @@ typedef struct asc_dvc_var {
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dma_addr_t overrun_dma;
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uchar scsi_reset_wait;
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uchar chip_no;
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- char is_in_int;
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+ bool is_in_int;
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uchar max_total_qng;
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uchar cur_total_qng;
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uchar in_critical_cnt;
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@@ -3754,7 +3747,7 @@ static int AscStartChip(PortAddr iop_base)
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return (1);
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}
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-static int AscStopChip(PortAddr iop_base)
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+static bool AscStopChip(PortAddr iop_base)
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{
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uchar cc_val;
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@@ -3765,9 +3758,9 @@ static int AscStopChip(PortAddr iop_base)
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AscSetChipIH(iop_base, INS_HALT);
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AscSetChipIH(iop_base, INS_RFLAG_WTM);
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if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
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- return (0);
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+ return false;
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}
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- return (1);
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+ return true;
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}
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static bool AscIsChipHalted(PortAddr iop_base)
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@@ -6453,7 +6446,7 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
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EXT_MSG ext_msg;
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EXT_MSG out_msg;
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ushort halt_q_addr;
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- int sdtr_accept;
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+ bool sdtr_accept;
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ushort int_halt_code;
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ASC_SCSI_BIT_ID_TYPE scsi_busy;
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ASC_SCSI_BIT_ID_TYPE target_id;
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@@ -6512,10 +6505,10 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
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if (ext_msg.msg_type == EXTENDED_MESSAGE &&
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ext_msg.msg_req == EXTENDED_SDTR &&
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ext_msg.msg_len == MS_SDTR_LEN) {
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- sdtr_accept = TRUE;
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+ sdtr_accept = true;
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if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
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- sdtr_accept = FALSE;
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+ sdtr_accept = false;
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ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
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}
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if ((ext_msg.xfer_period <
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@@ -6523,7 +6516,7 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
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|| (ext_msg.xfer_period >
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asc_dvc->sdtr_period_tbl[asc_dvc->
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max_sdtr_index])) {
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- sdtr_accept = FALSE;
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+ sdtr_accept = false;
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ext_msg.xfer_period =
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asc_dvc->sdtr_period_tbl[asc_dvc->
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min_sdtr_index];
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@@ -7111,7 +7104,7 @@ static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
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uchar cur_target_qng;
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ASC_QDONE_INFO scsiq_buf;
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ASC_QDONE_INFO *scsiq;
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- int false_overrun;
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+ bool false_overrun;
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iop_base = asc_dvc->iop_base;
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n_q_used = 1;
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@@ -7189,7 +7182,11 @@ static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
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((scsiq->q_status & QS_ABORTED) != 0)) {
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return (0x11);
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} else if (scsiq->q_status == QS_DONE) {
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- false_overrun = FALSE;
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+ /*
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+ * This is also curious.
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+ * false_overrun will _always_ be set to 'false'
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+ */
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+ false_overrun = false;
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if (scsiq->extra_bytes != 0) {
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scsiq->remain_bytes += scsiq->extra_bytes;
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}
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@@ -7262,23 +7259,23 @@ static int AscISR(ASC_DVC_VAR *asc_dvc)
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uchar host_flag;
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iop_base = asc_dvc->iop_base;
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- int_pending = FALSE;
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+ int_pending = ASC_FALSE;
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if (AscIsIntPending(iop_base) == 0)
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return int_pending;
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if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
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- return ERR;
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+ return ASC_ERROR;
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}
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if (asc_dvc->in_critical_cnt != 0) {
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AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
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- return ERR;
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+ return ASC_ERROR;
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}
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if (asc_dvc->is_in_int) {
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AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
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- return ERR;
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+ return ASC_ERROR;
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}
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- asc_dvc->is_in_int = TRUE;
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+ asc_dvc->is_in_int = true;
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ctrl_reg = AscGetChipControl(iop_base);
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saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
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CC_SINGLE_STEP | CC_DIAG | CC_TEST));
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@@ -7286,7 +7283,7 @@ static int AscISR(ASC_DVC_VAR *asc_dvc)
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if (chipstat & CSW_SCSI_RESET_LATCH) {
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if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
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int i = 10;
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- int_pending = TRUE;
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+ int_pending = ASC_TRUE;
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asc_dvc->sdtr_done = 0;
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saved_ctrl_reg &= (uchar)(~CC_HALT);
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while ((AscGetChipStatus(iop_base) &
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@@ -7308,7 +7305,7 @@ static int AscISR(ASC_DVC_VAR *asc_dvc)
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(uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
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if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
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AscAckInterrupt(iop_base);
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- int_pending = TRUE;
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+ int_pending = ASC_TRUE;
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if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
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if (AscIsrChipHalted(asc_dvc) == ERR) {
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goto ISR_REPORT_QDONE_FATAL_ERROR;
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@@ -7330,13 +7327,13 @@ static int AscISR(ASC_DVC_VAR *asc_dvc)
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} while (status == 0x11);
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}
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if ((status & 0x80) != 0)
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- int_pending = ERR;
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+ int_pending = ASC_ERROR;
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}
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}
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AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
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AscSetChipLramAddr(iop_base, saved_ram_addr);
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AscSetChipControl(iop_base, saved_ctrl_reg);
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- asc_dvc->is_in_int = FALSE;
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+ asc_dvc->is_in_int = false;
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return int_pending;
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}
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@@ -8423,7 +8420,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
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PortAddr iop_base;
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int sta;
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int n_q_required;
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- int disable_syn_offset_one_fix;
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+ bool disable_syn_offset_one_fix;
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int i;
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u32 addr;
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ushort sg_entry_cnt = 0;
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@@ -8488,7 +8485,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
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sg_entry_cnt_minus_one = sg_entry_cnt - 1;
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}
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scsi_cmd = scsiq->cdbptr[0];
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- disable_syn_offset_one_fix = FALSE;
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+ disable_syn_offset_one_fix = false;
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if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
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!(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
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if (scsiq->q1.cntl & QC_SG_HEAD) {
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@@ -8502,7 +8499,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
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}
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if (data_cnt != 0UL) {
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if (data_cnt < 512UL) {
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- disable_syn_offset_one_fix = TRUE;
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+ disable_syn_offset_one_fix = true;
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} else {
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for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
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i++) {
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@@ -8513,7 +8510,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
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}
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if (scsi_cmd == disable_cmd) {
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disable_syn_offset_one_fix =
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- TRUE;
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+ true;
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break;
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}
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}
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@@ -9058,7 +9055,7 @@ static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
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/* asc_dvc->init_state initialized in AscInitGetConfig(). */
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asc_dvc->sdtr_done = 0;
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asc_dvc->cur_total_qng = 0;
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- asc_dvc->is_in_int = 0;
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+ asc_dvc->is_in_int = false;
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asc_dvc->in_critical_cnt = 0;
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asc_dvc->last_q_shortage = 0;
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asc_dvc->use_tagged_qng = 0;
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@@ -9238,7 +9235,7 @@ static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
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int retry;
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retry = 0;
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- while (TRUE) {
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+ while (true) {
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AscSetChipEEPData(iop_base, data_reg);
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mdelay(1);
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read_back = AscGetChipEEPData(iop_base);
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@@ -9374,7 +9371,7 @@ static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
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int n_error;
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retry = 0;
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- while (TRUE) {
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+ while (true) {
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if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
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bus_type)) == 0) {
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break;
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@@ -9401,7 +9398,7 @@ static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
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warn_code = 0;
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AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
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AscStopQueueExe(iop_base);
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- if ((AscStopChip(iop_base) == FALSE) ||
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+ if ((AscStopChip(iop_base)) ||
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(AscGetChipScsiCtrl(iop_base) != 0)) {
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asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
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AscResetChipAndScsiBus(asc_dvc);
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@@ -11093,7 +11090,7 @@ static struct scsi_host_template advansys_template = {
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* must be set. The flag will be cleared in advansys_board_found
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* for non-ISA adapters.
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*/
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- .unchecked_isa_dma = 1,
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+ .unchecked_isa_dma = true,
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/*
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* All adapters controlled by this driver are capable of large
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* scatter-gather lists. According to the mid-level SCSI documentation
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@@ -11269,28 +11266,28 @@ static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
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switch (asc_dvc_varp->bus_type) {
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#ifdef CONFIG_ISA
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case ASC_IS_ISA:
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- shost->unchecked_isa_dma = TRUE;
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+ shost->unchecked_isa_dma = true;
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share_irq = 0;
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break;
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case ASC_IS_VL:
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- shost->unchecked_isa_dma = FALSE;
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+ shost->unchecked_isa_dma = false;
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share_irq = 0;
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break;
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case ASC_IS_EISA:
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- shost->unchecked_isa_dma = FALSE;
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+ shost->unchecked_isa_dma = false;
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share_irq = IRQF_SHARED;
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break;
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#endif /* CONFIG_ISA */
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#ifdef CONFIG_PCI
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case ASC_IS_PCI:
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- shost->unchecked_isa_dma = FALSE;
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+ shost->unchecked_isa_dma = false;
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share_irq = IRQF_SHARED;
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break;
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#endif /* CONFIG_PCI */
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default:
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shost_printk(KERN_ERR, shost, "unknown adapter type: "
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"%d\n", asc_dvc_varp->bus_type);
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- shost->unchecked_isa_dma = TRUE;
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+ shost->unchecked_isa_dma = false;
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share_irq = 0;
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break;
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}
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@@ -11309,7 +11306,7 @@ static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
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* For Wide boards set PCI information before calling
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* AdvInitGetConfig().
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*/
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- shost->unchecked_isa_dma = FALSE;
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+ shost->unchecked_isa_dma = false;
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share_irq = IRQF_SHARED;
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ASC_DBG(2, "AdvInitGetConfig()\n");
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