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@@ -2,6 +2,7 @@
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* Pistachio platform setup
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* Pistachio platform setup
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*
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*
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* Copyright (C) 2014 Google, Inc.
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* Copyright (C) 2014 Google, Inc.
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+ * Copyright (C) 2016 Imagination Technologies
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -9,6 +10,7 @@
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*/
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*/
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#include <linux/init.h>
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#include <linux/init.h>
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+#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_fdt.h>
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@@ -24,9 +26,38 @@
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#include <asm/smp-ops.h>
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#include <asm/smp-ops.h>
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#include <asm/traps.h>
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#include <asm/traps.h>
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+/*
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+ * Core revision register decoding
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+ * Bits 23 to 20: Major rev
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+ * Bits 15 to 8: Minor rev
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+ * Bits 7 to 0: Maintenance rev
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+ */
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+#define PISTACHIO_CORE_REV_REG 0xB81483D0
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+#define PISTACHIO_CORE_REV_A1 0x00100006
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+#define PISTACHIO_CORE_REV_B0 0x00100106
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+
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const char *get_system_type(void)
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const char *get_system_type(void)
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{
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{
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- return "IMG Pistachio SoC";
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+ u32 core_rev;
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+ const char *sys_type;
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+
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+ core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
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+
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+ switch (core_rev) {
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+ case PISTACHIO_CORE_REV_B0:
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+ sys_type = "IMG Pistachio SoC (B0)";
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+ break;
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+
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+ case PISTACHIO_CORE_REV_A1:
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+ sys_type = "IMG Pistachio SoC (A1)";
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+ break;
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+
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+ default:
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+ sys_type = "IMG Pistachio SoC";
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+ break;
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+ }
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+
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+ return sys_type;
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}
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}
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static void __init plat_setup_iocoherency(void)
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static void __init plat_setup_iocoherency(void)
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@@ -109,6 +140,8 @@ void __init prom_init(void)
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mips_cm_probe();
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mips_cm_probe();
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mips_cpc_probe();
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mips_cpc_probe();
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register_cps_smp_ops();
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register_cps_smp_ops();
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+
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+ pr_info("SoC Type: %s\n", get_system_type());
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}
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}
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void __init prom_free_prom_memory(void)
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void __init prom_free_prom_memory(void)
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