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@@ -264,10 +264,6 @@
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#define MSR_IA32_MC0_CTL2 0x00000280
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#define MSR_IA32_MC0_CTL2 0x00000280
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#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
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#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
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-/* 'SMCA': AMD64 Scalable MCA */
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-#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
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-#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
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-
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_EVNTSEL0 0x00000186
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#define MSR_P6_EVNTSEL0 0x00000186
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